Cisco ASIC Engineering Technical Leader 

United States, California, San Jose 

767406920

Your Impact:

You will gain hands-on experience in RTL verification and in-depth knowledge of SoC development cycle and the best industry practices, from specification through tape-out and lab validation.

You will:

• Architect block, cluster and top level DV environment infrastructure
• Create DV infrastructure from scratch for block, cluster and top level environments
• Maintain existing DV environments and enhance them for new features and requirements
• Ensure complete verification coverage through implementation and review of code and functional coverage
• Work closely with designers
• Support tests done with emulation
• Work closely with software teams and debug issues found during firmware development and be responsible for ASIC bring up

Minimum Qualifications:

• 10+ years ASIC design verification experience with a bachelor’s or master’s degree

• Prior experience with ASIC verification using UVM/System Verilog.
• Prior experience in verifying complex blocks, clusters and top level for SoC
• Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
• Prior experience with cross-functional teams, and possess the drive to learn and grow
• Prior experience on one or more protocols – PCIe, Ethernet, RDMA, TCP

Preferred Qualifications:

• Prior experience leading a team of engineers to complete verification of a complex block, cluster or chip-level design
• Lead verification for a complete SOC or ASIC i
• Prior Experience with Forwarding logic/Parsers/P4
• Formal verification (iev/vc formal) knowledge