Jobs in India

What you'll be doing:

• Leading Developer and ISV Strategy: Developing and implementing strategies to engage with developers and independent software vendors (ISVs) in India, collaborating with cross-functional teams like product, engineering, marketing, and sales.

• Understanding and Prioritizing GPU Acceleration Opportunities: Identifying and prioritizing applications and services in AI and Generative AI (Gen AI) that can benefit from GPU acceleration, while also understanding application workflows and architectural requirements for enabling such acceleration.

• Building Strategic Relationships: Establishing and nurturing relationships with key opinion leaders, researchers, product teams, and engineering leads at cloud service providers (CSPs) to ensure their success and incorporate their feedback into product development.

• Driving Developer Engagement: Creating strategic partnerships and building community by attending research conferences, hosting technical meetups and events, and engaging with the industry to showcase NVIDIA's GPU-accelerated solutions.

• Integrating NVIDIA Technology: Working to integrate NVIDIA GPU acceleration into CSP applications and solutions, while also staying aware of the competitive landscape.

• Startups Engagement: Leading initiatives to recruit and engage startups into programs like NVIDIA Inception, fostering co-innovation, and supporting their journey with NVIDIA's technology.

• Evangelizing NVIDIA's AI Strategy: Representing NVIDIA at industry events and partner meetings to communicate and promote the company's AI vision to both technical and business audiences.

• Driving training initiatives and Operations: Working with universities, training partners and ministries to drive NVIDIA SDK, libraries adoption .

What We Need To See:

• Bachelors degree or equivalent experience in Computer Science, Applied Mathematics, or related engineering field (Ph.D. or Masters preferred).

• 12+ overall years of experience

• 6+ years of meaningful experience in a technical leadership role.

• World-class communication skills with a demonstrated ability to articulate a value proposition to technical and non-technical audiences.

Ways to stand out from the crowd:

• Experience working on AI Deep Learning and Machine Learning Applications, AI Model Training/Inferencing and other GPU related technologies and application domain.

• Strong technical understanding of Data Analytics, Conversational AI, Embedded System/Jetson.

• Strong analytical, problem solving, and negotiation skills and the ability to use data analysis to support strategic decisions

What you’ll be doing:

• Own ASIC verification of IP/Cluster for complicated designs in RTL.

• Work with HW architects and designers to make the right implementation choices.

• Interact with the Performance verification teams to augment verification through dynamic simulations and/or Formal verification techniques.

• You will work with the specifications and ensure functional and code coverage of all the RTL which you will verify.

• Partner with and enable FPGA and S/W teams to ensure that S/W is tested.

• Be involved with post-silicon verification and debug.

What we need to see:

• BS / MS or equivalent experience.

• 2+ years of design experience.

• Experience in ASIC verification of complex design units for at least one or two projects.

• Background with design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB).

• Exposure to System Verilog and UVM based methodology for ASIC verification is highly desired.

Ways to stand out from the crowd:

• Knowledge of Memory controllers or prior experience with verification of IP/clusters involving access to Memory.

• Good debugging and problem solving skills.

• Scripting knowledge (Python/Perl/shell).

• Good interpersonal skills and ability & desire to work as a part of a team.

What you will be doing:

• Architect multi-GPU system topologies for scale-up and scale-out configurations, balancing AI throughput, scalability, and resilience.

• Define, modify and evaluate future architectures for high-speed interconnects such as NVLink and Ethernet co-designed with the GPU memory system.

• Collaborate with other teams to architect RDMA-capable hardware and define transport layer optimizations for GPU-based large scale AI workload deployments.

• Use and modify system models, perform simulations and bottleneck analyses to guide design trade-offs.

• Work with GPU ASIC, compiler, library and software stack teams to enable efficient hardware-software co-design across compute, memory, and communication layers.

• Contribute to interposer, package, PCB and switch co-design for novel high-density multi-die, multi-package, multi-node rack-scale systems consisting of hundreds of GPUs.

What we need to see:

• BS/MS/PhD in Electrical Engineering, Computer Engineering, or equivalent area.

• 8 years or more of relevant experience in system design and/or ASIC/SoC architecture for GPU, CPU or networking products.

• Deep understanding of communication interconnect protocols such as NVLink, Ethernet, InfiniBand, CXL and PCIe.

• Experience with RDMA/RoCE or InfiniBand transport offload architectures.

• Proven ability to architect multi-GPU/multi-CPU topologies, with awareness of bandwidth scaling, NUMA, memory models, coherency and resilience.

• Experience with hardware-software interaction, drivers and runtimes, and performance tuning for modern distributed computing systems.

• Strong analytical and system modeling skills (Python, SystemC, or similar).

• Excellent cross-functional collaboration skills with silicon, packaging, board, and software teams.

Ways to stand out from the crowd:

• Background in system design for AI and HPC.

• Experience with NICs or DPU architecture and other transport offload engines.

• Expertise in chiplet interconnect architectures or multi-node fabrics and protocols for distributed computing.

• Hands-on experience with interposer or 2.5D/3D package co-design.

We are now looking for passionate, highly motivated and creative individuals to be part of our automotive verification team. As a verification owner, you will work on projects that will define the next generation of automotive chips and systems. You will get firsthand exposure to high performance CPU and Memory sub-systems, NOC based Interconnect Fabric, High speed IO's and many other leading technologies deployed in our Tegra chips.

What you will be doing:

You will be responsible for creation of "state of the art" UVM based verification test benches and methodologies to verify complex IP's and Sub-systems. You will also get to work on System level verification using C/C++. During the course of a project you would end up driving the following aspects of verification for your unit:

• Architect the testbenches and craft verification environment using UVM methodology

• Define test plans, tests and verification infrastructure for modules, clusters and system

• Build efficient and reusable bus functional models, monitors, checkers and scoreboards

• Implement functional coverage and own verification closure

• Work with architects, designers, FPGA and post-silicon teams to ensure that your unit is robust

What we need to see:

You should be BTech/MTech with 5+ years of experience in verification closure of complex Unit, Sub-system or SOC level verification. If you have experience in at least a few of the following domains, we will have an excellent match for our needs:

• CPU verification, Memory controller verification, Interconnect verification

• High Speed IO verification (UFS/PCIE/XUSB)

• 10G/1G Ethernet MAC and Switch

• Bus protocols (AXI/APB)

• System functions like Safety, Security, Virtualization and sensor processing

• Experience in the latest verification methodologies like UVM/VMM

• Exposure to industry standard verification tools for simulation and debug is a requirement

• Exposure to Formal verification would be excellent

• Good debugging and analytical skills.

• Good interpersonal skills, ability to work as an excellent teammatewith e