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Details
Key Qualifications
- You will have 10+ years' of experience in all aspects of ASIC implementation including Synthesis, DFT insertion, Floorplanning, Clock and Power distribution, Place and Route and all aspects of timing, electrical and physical signoff.
- Proven track record to work with multi-functional teams
- Mentor junior engineers, guide them in problem solving and lead all aspects of signoff
- Technical leadership, drive PPA recipes across the team
- Work with FE and Architecture team to understand chip architecture and drive physical aspects early in the design cycle
- Familiar with multiple voltage domains, power gating and low power design techniques
- Familiar with hierarchical design approaches, top-down design, budgeting, timing and physical convergence
- Experience with large designs (>20M gates) with frequencies in excess of 1GHz utilizing innovative technologies
- Drive methodologies and “best known methods” to streamline physical design work, develop guidelines and checklists, drive execution, and supervise progress
- Resolve design and flow issues related to physical design, identify potential solutions and drive execution
Description
In this role you will work closely with multi-functional and product teams to come up with efficient chip architecture taking into account physical constraints early in the design cycle. You will own all physical design aspects of your partition including signoff as well as provide early RTL feedback to get efficient Floorplans and push best in class PD construction and optimization recipes for performance, power and Area (PPA). You will also collaborate to drive methodologies and “best known methods” to streamline PD work and develop guidelines and checklists.Are you a detail oriented designer ready to solve complex technical problems? Are you ready to mentor others and join a best-in-class engineering team to help chart the future of Apple's ecosystem? If so, we are looking to hear from you!
Education & Experience
MSEE or equivalent is required
