Cisco ASIC Engineering Technical Leader 

United States, California, San Jose 

39496391

The application window is expected to close on: May 20th, 2025.

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

Your Impact

• You will be leading the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips.
• Design & implement robust and reusable RTL with CDC/RDC considerations
• Spec comprehensive CDC/RDC check flows and work with CAD team to implement
• Review and approve CDC/RDC constraints and waivers
• Perform static glitch analysis
• Improve design with prevention of static glitch hazard

Minimum Qualifications

• Bachelor's or Master's degree on Electrical Engineering with at least 10 years of experience on ASIC chip design
• Prior experience withRTLdevelopment on
  Asynchronous design
• Prior experience on CDC/RDC concepts and relevant design implementation
• Prior experience on maintaining CDC/RDC flow and signing-off constraints and waivers
• Prior work with static glitch hazards and experience on the relevant analysis on synthesis optimized gate netlists

Preferred Qualifications

• Experiences on Static Timing Analysis
• Experiences on VCS simulation SVA (SystemVerilog Assertions)