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Cisco ASIC Engineering Technical Leader 
United States, California, San Jose 
388832037

Today

The Application window has been extended and expected to close on 05/09/2025.

The job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

What You'll Do

Be part of the development organization as an ASIC Engineering Technical Leader with primaryfocus on RTL Design.

  • Create micro-architecture specifications and participate in reviews
  • Implement Verilog RTL to meet timing and performance requirements.
  • Help define, evolve, and support our design methodology.
  • Collaborate with the verification team on as-needed basis to address design bugs and close code coverage.
  • Work closely with physical design team to close design timing and place-and-route issues
  • Triage, debug, and root cause simulation, software bring-up, and customer failures.
  • Perform diagnostic and post silicon validation tests in the lab.

Who You'll Work With

You will work with front-end RTL Design and Verification teams and Architects to understand chip architecture. You’ll work with SDK and Software teams as part of ASIC development to create a seamless handshake between hardware and software functionalities and qualify use-case requirements. You’ll also work with systems-testing teams as part of post-silicon validation efforts to bring-up, debug and qualify the ASIC in deployment-mode applications.


Minimum Qualifications:

  • Bachelor's or a Master’s Degree in Electrical or Computer Engineering, with 10+ years of related work experience
  • Prior experience with developing Micro-Architecture for blocks
  • Prior experience with Verilog/System Verilog
  • Prior experience with Clock Domain, Reset Domain Crossing issues, and Low-Power Design Techniques
  • Prior experience with simulators and waveform debugging tools
  • Prior experience working with Linting, Synthesis and Static Timing Analysis tools
  • Prior experience with Verification methodologies including experience developing testbenches, writing System Verilog Assertions and debugging Netlist simulations

Preferred Qualifications:

  • Understanding of Networking technologies and concepts.,
  • Experience with ARM protocols (AXI, CHI, APB. AHB) and exposure to ARM CPU’s is desirable.
  • Design experience with Ethernet MAC, DDR/LPDDR, PCIE and DMA controllers is a plus.
  • Experience with Integrating 3rdparty IP’s into SoC is desirable
  • Scripting experience (Python, Perl, TCL, shell programming) highly desirable.
  • Experience with Emulation and Formal Verification tools is a plus.