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Cisco ASIC Engineering Technical Leader United States, California, San Jose 569853151
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This is an onsite role and will require working out of the Milpitas/San Jose office location.Application for this role is expected to close 4/25/2025
Who You'll Work With:You will be in the Silicon One development organization as a senior DFT verification lead in San Jose, CA. You will work with Front-end RTL teams, backend physical design teams to understand chip architecture and drive high-quality DFT verification.
What You'll Do:
- Responsible for thorough test planning and development of test benches to verify comprehensive Design-for-Test (DFT) architecture that supports ATE screening, in-system test, debug and diagnostics needs of the design
- Work closely with the design/design-verification and PD teams to enable the integration and validation of the test logic in all phases of the implementation and post silicon validation flows.
- Work with the team on Innovative Hardware DFT & test strategy aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug methodologies and standards.
- Work with the team on DFT challenge identification, cross-functional solution brainstorming and implementation plan development, and lead junior engineers to deliver expected implementations on schedule.
- The job requires the candidate to have the ability to craft solutions and debug with minimal mentorship.
- Bachelor's or Master’s Degree in Electrical or Computer Engineering required with at least 7 years of experience.
- Prior experience in test planning based on complex design specification.
- Prior experience in testbench development using System Verilog.
- Prior Debugging experience using DVE/Verdi.
- Scripting skills: Tcl, Python/Perl.
- UVM and advanced System Verilog knowledge.
- Knowledge about JTAG protocol, scan architecture, MBIST and boundary scan.
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