Cisco ASIC Engineering Technical Leader 

United States, California, San Jose 

569853151

What You'll Do

• Would be working to validate system architecture and design implementation micro-architecture to make sure final products would meet performance expectations.
• Gather information from underlying system specifications and asking detailed probing questions as needed to construct fairly accurate and efficient models.
• Partition overall systems to be modelled into lower level blocks while keeping modularity, re-use and test requirements in mind.
• Construct OMNeT++ models for underlying blocks that will stitch together to form overall target system to be validated.
• Define and execute test plans to validate system performance goals.
• Compile test results, summarize important findings, rationalize any unexpected observations, offer insights on how to improve performance etc.

Minimum Qualifications:

• Bachelor’s or Master’s degree with8+ years of hands-on experience with ASIC micro-architecture or modeling
• Prior experiencewith C++ programming and debugging complex programs.
• Prior experiencewith network switch fabric concepts, queuing, scheduling, buffer management, congestion handling etc.
• Prior experience with cross-functional teams, and possess the drive to learn and grow
• Prior experience building test benches from scratch, hands on experience with System Verilog constraints, structures and classes.
• Prior experience with cross-functional teams

Preferred Qualifications:

• Experience with modeling systems and network switches, particularly with OMNeT++ would be a plus.
• Domain experience on one or more protocols – PCIe, Ethernet, RDMA, TCP