Nvidia Senior ASIC Physical Design Timing Engineer 

United States, Texas 

586872966

What you'll be doing:

• Drive physical design and timing of high-frequency and low-power CPU, GPU, DPU and SoCs at block level, cluster level, and/or full chip level.

• Help in driving frontend and backend implementation from RTL to gds2, including synthesis, equivalence checking, floor-planning, timing constraints, timing and power convergence, and ECO implementation.

• Work in a cross-functional environment interacting with multiple teams.

• Apply knowledge and experience to improve the convergence flows working with the Methodology Team.
  

What we need to see:

• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years experience or MS (or equivalent experience) with 2+ years experience in Synthesis and Timing

• Hands-on experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.

• Expertise in analyzing and converging crosstalk delay, noise glitch, andelectrical/manufacturingrules in deep-sub micron processes.

• Expertise in physical design and optimization e.g., placement, routing, cell sizing, buffering, logic restructuring, etc. to improve timing and power, along with a background in implementing them through ECOs.

• Background in logic synthesis and equivalence checking/FV required.

• Expertise and in-depth knowledge of industry standard EDA tools.

• Proficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc.
  

Ways to stand out from the crowd:

• Background in high-performance designs, such as CPUs, GPUs or Network processor implementation and timing convergence, is a plus

• Good understanding of hardware architecture and skills in RTL/logic design for timing closure, specifically experience in critical timing path planning and crafting.

• Understanding of DFT logic and experience with DFT timing closure for various modes e.g., scan shift and capture, transition faults, BIST, etc.

• Knowledge of deep sub-micron technology and associated process variations effects, including modeling and converging considering process variations.

• Knowledge in circuits, SPICE simulations, and/or transistor level STA as well as Experience in methodology and/or flowdevelopment/automation.