Nvidia Senior ASIC Timing Engineer 

United States, California 

697018243

What you'll be doing:

• Develop and execute timing closure plans for NVIDIA's next generation of CPU, GPU or SOC designs.

• Owning STA of large subsystems and full chip designs or at block-level with additional responsibilities for block levelsynthesis/optimization

• You will be responsible for all aspects of timing including, timing analysis and closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs.

• Finding the right tradeoffs and balance between frequency andpower/area/congestions/yield/etc.

What we need to see:

• BS (or equivalent experience) in Electrical or Computer Engineering with 5+ years experience or MS (or equivalent experience) with 2+ years experience in ASIC Design and Timing

• Great understanding of timing and physical design fundamentals

• Hands-on experience in ASIC timing closure at full chip or subsystem level with a good understanding of RTL/logic design skills as well as physical design/circuit skills for timing closure.

• Excellent problem solving and debugging skills for timing issues, timing constraints and clocking.

• Expertise in STA tools and methodologies for timing closure with a good understanding of deep sub-micron process effects.

• Strong background and experience in timing constraints generation, analysis and debug including SDCs.

• Knowledge of timing corners/modes, process variations and signal integrity related issues and modeling.

• Familiarity with logic synthesis, equivalence checking, DFT, Floorplanning, Place & Route, and ECO implementation methodology and tools

• Proficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc. and ability to understand and improve existing flows and methodologies.

• Strong interpersonal and communication skills and ability to collaborate with cross-functional teams.

Ways to stand out from the crowd:

• Deep understanding of CPU, GPU, SOC architecture and designs as well as ability to plan and craft timing critical paths.

• Background and expertise in high frequency design closure at the full chip or major subsystem level..

• Ability to develop new methodologies/flows as well as workflows to aid timing convergence.