Nvidia Senior ASIC Engineer Timing 

United States, California 

543625988

What you'll be doing:

• You will drive physical design of high-frequency and low-power CPUs, GPUs, SoCs at block level, cluster level, and/or full chip level, with a focus on netlist-related aspects such as equivalence checking, asynchronous checking including clock domain crossing checks and MTBF analysis, logic synthesis, netlist quality checks, etc.

• Help in all aspects of physical design, such as driving timing convergence, timing constraints generation and management, and ECO generation and implementation.

• Work in a cross-functional environment interacting with multiple teams.

• Work on project execution as well as methodology improvements.

What we need to see:

• BS (or equivalent experience) in Electrical or Computer Engineering with 5 years’ experience or MS (or equivalent experience) with 2+ years’ experience in ASIC Design and Timing

• Great understanding of timing and physical design fundamentals

• Hands-on experience in ASIC timing closure at full chip or subsystem level with a good understanding of RTL/logic design skills as well as physical design/circuit skills for timing closure.

• Excellent problem solving and debugging skills for timing issues, timing constraints and clocking.

• Expertise in STA tools and methodologies for timing closure with a good understanding of deep sub-micron process effects.

• Strong background and experience in timing constraints generation, analysis and debug including SDCs.

• Knowledge of timing corners/modes, process variations and signal integrity related issues and modeling.

• Familiarity with logic synthesis, equivalence checking, DFT, Floorplanning, Place & Route, and ECO implementation methodology and tools

• Proficiency in programming and scripting languages, such as, Perl, Tcl, Python, etc. and ability to understand and improve existing flows and methodologies.

• Strong interpersonal and communication skills and ability to collaborate with cross-functional teams.

Ways to stand out from the crowd:

• Deep understanding of CPU, GPU, SOC architecture and designs as well as ability to plan and craft timing critical paths.

• Background and expertise in high-speed and low-power design closure.

• Ability to develop new methodologies/flows as well as workflows to aid timing convergence.