Nvidia Senior ASIC Timing Engineer 

United States, California 

124275718

What you'll be doing:

• You will be responsible for all aspects of timing including, timing analysis and closure, timing environment, setting up constraints and defining the timing methodology for the next generation of designs. This includes working with place and route to understand and implement around their constraints.

• Finding the right tradeoffs and balance between frequency andpower/area/congestions/yield/etc.

• Work on all aspects of DFT/Test timing such as timing constraints, timing analysis, timing convergence, and ECO implementation.

What we need to see:

• Hold a BS in Electrical or Computer Engineering or equivalent experience.

• 8+ years experience in Physical design/Timing.

• Experience in full-chip/sub-chip Static Timing Analysis (STA), timing constraints generation and management, and timing convergence.

• In-depth understanding of multiplexed scan logic and constraints.

• Expertise in physical design, optimization, and ECO implementation e.g. cell sizing, buffering, vt swap.

• Hands-on knowledge of industry standard Timing/STA EDA tools.

• Proficiency in programming and scripting languages, such as TCL and Python.

Ways to stand out from the crowd:

• Experience with DFT timing closure for various modes e.g. scan shift, scan capture, transition faults, BIST, etc.

• Knowledge of clocking and clock controls in DFT modes.

• Experience in methodology or flow development.