Cisco ASIC Physical Design Engineer 

United States, Massachusetts 

986521977

Acacia Communications designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks.

You will be a key member of Acacia’s Physical Design team working on next generation 100G-1T coherent optical communications products. The senior physical design engineer will be focused on delivering highly-complex ASICs in advanced technology nodes that are used in these next-generation telecom systems.

You will collaborate with Acacia’s ASIC and Hardware teams in the engineering organization to deliver tape-out quality physical designs.

You will work closely with RTL designers to debug and root-cause physical implementation issues related to design, tools, etc. and arrive at a feasible solution through the augmentation of input and design collateral.

You will work with the ASIC physical design team to enhance and continuously improve the physical design implementation flow.

You are enthusiastic about delivering high quality physical designs under tight tape-out schedules. You are detail oriented, high energy and the drive to get things done. You love to solve difficult problems and derive tremendous satisfaction in helping others while contributing to the overall success of the project.

• BSEE, or equivalent, with 7+ years of experience in ASIC development or MSEE, or equivalent, with 4+ years of experience in ASIC development
• At least 7 years of professional engineering experience, including experience in advanced technology nodes: 28nm, 16nm and below
• 5+ years of experience with industry standard CAD methodologies from Cadence, Synopsys and/or Mentor
• 5+ years of experience with floor planning & partitioning, synthesis, place & route, static timing analysis (STA), formal equivalence check, Clock Tree Synthesis, timing closure, signal integrity, physical verification DRC/LVS
• 5+ years of scripting experience with Perl and TCL or equivalent
• Execution of ASICs from product definition to production release

• Experience with power analysis, electromigration, IR signoff, process corner decisions, power grid analysis.
• Ability to manage stakeholders across analog and digital teams while interfacing with EDA vendors on issues/features/enhancements.
• Solid analytical, communication and presentation skills
• Self-motivated and the ability to drive without supervision.

We tackle whatever challenges come our way. We have each other’s backs, we recognize our accomplishments, and we grow together. We celebrate and support one another – from big and small things in life to big career moments. And giving back is in our DNA (we get 10 days off each year to do just that).