דרושים Asic Physical Design Engineer ב-Cisco ב-United States, Massachusetts

• Lead the design and implementation of functional and non-functional UI features .
• Mentor and coach junior frontend developers.
• Build advanced product integrations and cross-product AI-driven interfaces .
• Work primarily with React/Angular , while collaborating closely with backend and infra teams.
• Contribute to UI Ops and CI/CD optimization for frontend delivery.

• 5+ years of relevant frontend development experience.
• Solid understanding of React, Angular, Webpack, RSPack (or equivalent) .
• Solid understanding of design libraries and SCSS/HTML
• Familiarity with UI Ops and continuous delivery practices.
• Backend development experience – an advantage.
• Up to date with AI tools and methodologies .
• A perpetual learner with a passion for clean, scalable, and user-friendly design.

The application window is expected to close on: 8/15/25.

Job posting may be removed earlier if the position is filled or if sufficient number of applications are received.

You will collaborate with Acacia’s ASIC and Hardware teams in the engineering organization to deliver tape-out quality physical designs.

You will work closely with RTL designers to debug and root-cause physical implementation issues related to design, tools, etc. and arrive at a feasible solution through the augmentation of input and design collateral.

You will work closely with Back-end team on timing signoff for seamless physical design closure.

You will work with the ASIC physical design team to enhance and continuously improve the physical design implementation flow.

• BS in Electronics/Electrical Engineering or equivalent with 5+ years of experience in the telecommunications industry
• At least 5 years of professional engineering experience, including experience in advanced technology nodes: 5nm, 5/4nm, 3nm, and below
• Experience with industry standard CAD methodologies from Cadence, Synopsys and/or Mentor
• Experience with floor planning & partitioning, synthesis, place & route, static timing analysis (STA), formal equivalence check, Clock Tree Synthesis, timing closure, signal integrity, physical verification DRC/LVS
• Scripting experience with TCL, Python and Perl
• Execution of ASICs from product definition to production release

• Experience with power analysis, electromigration, IR signoff, process corner decisions, power grid analysis.
• Ability to manage stakeholders across analog and digital teams while interfacing with EDA vendors on issues/features/enhancements.
• Solid analytical, communication and presentation skills
• Self-motivated and the ability to drive without supervision.

Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received.

You are a high-energy FGPA Design engineer who loves to work on complex communications products. You are a team player with a startup mentality who loves to challenge the status quo with creation and innovation. You can figure things out by yourself, but you are comfortable to participate in our friendly and team-oriented collaboration approach to learn from others. You are not shy to point out how we can be more effective as a team, and yet you are open to similar suggestions by your team members to foster mutual growth for all.

• Design/Verify FGPAs For Acacia's Product and Evaluation platform
• Write Python routines for Test Development and Automation
• Contribute to FPGA Emulation of ASIC Blocks
• Contribute to our custom ASIC RTL code

Minimum Qualifications (Provide up to five (5) bullet points- these should be clearly defined, objective, non-comparative, relevant, and quantifiable to appropriately evaluate applicants – not including soft skills):

• Bachelors +8 years of experience, or Masters +6 years of experience, or PHD +3 years of experience of related experience or higher with minimum
• 5+ years of FPGA design and verification experience
• Experience in Verilog RTL coding and synthesis for FPGAs
• Experience with Python and Linux
• Experience designing interfaces with Processors, SPI & I2C devices, MDIO, high speed SERDES, etc.
• Experience in Xilinx® design tool chain for design, place, and route (ISE®, Vivado® suite)

Preferred Qualifications (Provide up to five (5) bullet points: these can include soft skills)

• C/C++ and experience coding with embedded MCUs
• Experience in designs and timing closure with multiple clock domains
• Experience work in labs and experience with test equipment to help with board level and FPGA bring up
• Experience with analog components (OpAmps, DACs/ADCs, etc.)
• Experience implementing digital control loops and DSP functions
• Experience with Xilinx FPGA families such as Ultrascale+
• Experience with Synopsys VCS simulation and Synplify® synthesis tools for FPGAs
• Expertise in creating FPGA implementations from ASIC RTL code
• Expertise in digital design of standard cell ASICs
• Experience presenting technical information to technical and non-technical audiences.