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Apple Emulation Verification Engineer United States, Oregon, Beaverton 876781507
09.06.2025
- Minimum of BS + 3 years relevant industry experience.
- Understanding of the tool flow from RTL to Emulation is a huge plus
- Good understanding of any Standard Emulator (Palladium, Veloce, Zebu) OR FPGA (Xilinx, Altera) flow
- Proven design verification skills
- Experience in writing Synthesize-able SystemVerilog/Verilog code and SystemVerilog assertions
- Experience with System Verilog verification environments including C/C++ DPI, UVM
- Experience with writing and debugging test FW
- Experience on any Scripting (Perl/Python/TCL)
- Excellent analytical and debug skills
- Experience in UVM Acceleration is plus
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