Nvidia Principal Software Engineer RTL Optimization Tools 

United States, Texas 

199969318

What you’ll be doing:

• Invent new methods to enable parallel, graph-based RTL traversal, analysis, and manipulation.

• Devise strategies for rapidly analyzing the impact of RTL changes on data path latency, power, and impact to DFT, clocking, and power delivery.

• Explore high performance algorithms for clustering, min cost tree covering (technology mapping), datapath implementation and other details of logic synthesis, especially that efficiently incorporate human insight.

• Explore use of LLMs (Large Language Models), GNNs (Graph Neural Networks), GANs (Generative Adversarial Networks), and Reinforcement Learning for suggesting or automatically implementing RTL modifications.

• As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment. That translates to a bigger picture view of your work, going beyond simply responding to user requests to instead actively driving the roadmap of increasing hardware design productivity.

What we need to see:

• MS or PhD in Electrical Engineering or Computer Science or equivalent experience

• 12+ years of relevant experience in CAD software and VLSI hardware design

• Demonstrated ability in software development with C++, particularly in algorithm development related to graph traversal, pattern matching, and optimization

• Fluency in RTL design, including Verilog and SystemVerilog code, as well as general hardware design concerns such as scan chain insertion, MBIST, clock and power distribution, and bus architectures

• Familiarity with related EDA techniques, including logic synthesis, global route, static timing analysis, and SAT solvers

• Strong communication and interpersonal skills

Ways to stand out from the crowd:

• Previous work experience including both software and hardware roles, especially involving SOC/IP integration or RTL design

• Experience with common EDA building blocks, such as Verific for Verilog parsing, Espresso for logic minimization, and various other components for logic rewriting, tree coverage, SAT solvers, and combinatorial optimization

• Experience in high performance software design including multithreading, distributed computing, efficient memory and I/O use, etc.

• Experience with various machine learning techniques for analysis, optimization, and code generation