ARM Staff Design Verification Engineer - Cache Coherency 

United States, Texas, Austin 

151876123

Arm System IP enables designers to build Arm AMBA systems that are high performance, power efficient and reliable. Configurable for many different applications, System IP is the right choice for your system whether it is a high-efficiency IoT endpoint or a high-performance server SoC.

• Build and maintain detailed verification plans/strategies for our next generation interconnect designs.
• Work alongside architects and designers to debug and develop new features balancing the needs of multiple partners in our product development cycle.
• Architect and develop sophisticated and efficient SystemVerilog/UVM based test benches.
• Debug functional regression failures, close coverage and drive improvements.

• Bachelors, Masters or PhD in Electrical/Computer Engineering or Computer Science
• 8 to 15 years of experience in verification/RTL design.
• Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI).
• Previous experience in specification, creation, and debug of System Verilog/UVM constrained-random testbenches.
• Demonstrated ability, experience and successful track record verifying sophisticated designs in the area of cache coherency, multi-processor designs and memory sub-systems.
• Strong software engineering skills including understanding of object-oriented programming, data structures, and algorithms.
• Proficiency with functional coverage verification methods.
• Strong debug skills and ability to use modern techniques, methodologies and EDA tools.

• Knowledge of high speed protocols such as PCI Express (PCIe), SATA, USB and Ethernet.
• Excellent knowledge of scripting languages such as Python or Perl.
• Experience in Formal Verification techniques is a plus.