דרושים Principal Signal Integrity Engineer – Advanced Packaging ב-Marvell ב-ארגנטינה

What You Can Expect

• Perform full-chip and block-level static timing analysis for advanced ASIC designs
• Develop, maintain, and optimize timing constraints, methodologies, and automation scripts
• Own timing closure across all stages of the design flow: RTL, synthesis, physical implementation, and signoff
• Debug and resolve complex timing violations and drive design fixes
• Collaborate closely with design, synthesis, and physical design teams to meet performance, power, and area (PPA) goals
• Provide guidance on design partitioning, floorplanning, and timing budgeting strategies
• Contribute to design reviews and provide expert insights for design improvements

What We're Looking For

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related discipline
• 8+ years of hands-on experience in STA and timing closure for large-scale ASIC designs
• Strong proficiency with EDA tools such as Synopsys PrimeTime, PrimeTime SI, and/or Cadence Tempus
• Deep understanding of timing concepts, constraints development, and signoff methodologies
• Demonstrated success in driving complex designs to timing closure
• Excellent problem-solving skills and strong attention to detail
• Strong communication skills and proven ability to work effectively in a collaborative team environment

• Preferred Experience:

• Familiarity with scripting languages such as Tcl, Perl, or Python
• Experience with hierarchical timing andmulti-mode/multi-corner(MMMC) analysis
• Knowledge of data center ASIC architecture or high-performance computing systems

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

What You Can Expect

• Joint design team and own a piece of the design.

• Verify analog IC design using spice simulations

• Run Electromigration/IR drop (EMIR) on analog IC layout

• Run co-simulation between digital and analog designs

• Run Static Timing Analysis (STA) on high speed analog IC design

• Develop and enhance flows that support and facilitate robust analog IC design

What We're Looking For

Students have to be in last year of a 5/5.5 year Engineer course at UTN/UNC/IUA or doing Master/PhD in Electrical Engineer at any university of Argentina.• Intuitive and analytical understanding of transistor level and CMOS circuit design
• Experience in Cadence schematics capture, simulation and layout
• Ability to define and adhere to project schedules
• Ability to have effective written and verbal communication skills
• Ability to write behavioral models for both and analog and digital circuits is a plus

What You Can Expect

• Collaborating with cross-functional teams: Work closely with circuit design, applications engineering, packaging technology, and board design teams to define and implement system interconnects that meet both internal specifications and customer requirements.
• Conducting simulations and analysis: Perform SI/PI simulations and analysis to predict and mitigate potential issues in the design phase.
• Developing SI/PI design rules: Create and maintain design rules for floorplan, RDL, bump patterns, 2.5D/2D package, and PCB layouts to ensure signal and power integrity across the system.
• SI/PI modelrelease: Release
• Providing technical support: Offer technical support and guidance to other teams and customers regarding SI/PI issues and best practices.

What We're Looking For

• Bachelor’s degree in electrical engineering and 8+ years of related professional experience or Master’s degree/PhD in electrical engineering with 5+ years of experience.
• Solid transmission line and EM background is a must.
• Must have good knowledge aboutinterposer/package/PCBdesign rules, routing feasibility and SI/PI design consideration.
• Experiences in die-to-die interposer, package and PCB high density trial routing study by using Cadence tool such as APD or PCB editor is good plus.
• System-level SI/PI simulation experience such as DDR/NAND and PCIe/Ethernet is preferred.
• Always do the right thing and represent Marvell with ethics and integrity.

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

What You Can Expect

As an Analog Layout Engineer at Marvell, you’ll be working with global teams in Argentina, Singapore, the U.S., and throughout Europe. You’ll receive a schematic from an Analog IC Designer. You will then take that schematic and use a CAD tool to graphically design the layers of that schematic. Then, you run verifications on the design using Cadence Virtuoso, refine and debug as needed in concert with the designer, and both of you keep iterating the design until it meets the desired specifications.
Each project can last from a couple months to a year and a half. You will likely work on just one project in that time, but may be asked to switch to something else if priorities change. Your flexibility is appreciated.

What We're Looking For

• Have a fundamental understanding of electrical concepts, likely acquired through a degree in Electrical Engineering (graduate or undergraduate).
• Have experience in PCB design, with a good understanding of verification tools such as Layout vs Schematic and Design Rule Check.
• Know how to use CAD tools to create the implementation and microelectronic layers in design that go beyond the schematics.
• Have excellent communication skills to give status updates to your team, present to global teams in different time zones, and share information with many different levels of personnel at Marvell. Fluency in English is required.
• It will be valued to have taken courses in analog integrated circuit design, VLSI, analog layout design, or similar.

What You Can Expect

• Analyze the and extract Spec, createcomprehensivetest plan and coverage plan.
• Contribute to the development of UVM components, ENV, Coverage model, and Assertion protocol checkers.
• Write testcases, run simulation, regression.
• Debug and propose bug fixings.
• Merge, analyze and improve the coverage results.
• Run GLN/SDF simulation and propose ECO fixings.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering or related fields and 2-3 years of related professional experience, or Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 1-2 years of experience.
• Experience with Verilog and SystemVerilog, preferably with UVM.
• Basic proficiency with C/C++.
• Experience with scripting languages, e.g., Python or Perl.
• Working knowledge of the Linux operating system.
• English Proficiency is a plus.

What You Can Expect

What We're Looking For

• Candidate MUST be pursuing a degree in Electronic Engineering or related technical field(s).

• Have less than 5 final exams to graduate or less than one year to finish the career.

• Knowledgeofobject-orientedprogramming(OOP)

• Basic concepts aboutverificationtoolssuch asVerilogandSystemVerilogfordigitalsystemdescriptionandverification.

• SomeexperiencewithPythonscriptingforthecreationofmodelstoreduceerrorsandsimplifyreusability

What You Can Expect

What We're Looking For

• B.S. in Electrical or Computer Engineering (or related) required, MSEE and/or MBA preferred.
• 15+ years of relevant semiconductor experience with solid understanding of semiconductor compute (CPU, GPU, FPGA) technologies and dynamics.
• Excellent communication, interpersonal and presentation skills to all levels of the corporation, as well as partners and customers, with emphasis on persuasion and influence.
• Can-do self-starter with strong cross-functional leadership skills.
• Strong product management experience including defining products, developing MRDs, and driving design and package engineering analysis.
• Must have experience in a customer-facing role. The candidate must have the necessary communications skills and experience to be able to interface effectively and manage product expectations at customer.
• Experience in compute market and Product Marketing, Business Analysis. Experience with AI devices and AI system designs is a strong plus.
• Comprehensive background in semiconductor design necessary to evaluate product tradeoffs for performance, manufacturing cost, power and total development cost. Familiarity with key system elements of AI, CPU, GPU, FPGA and compute products in order to evaluate product tradeoffs.
• Strong work ethic, extreme ownership, and adaptability to rapidly changing environments.

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at