Marvell Principal Signal Integrity Engineer – Advanced Packaging Argentina 552225428
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What You Can Expect
Joint design team and own a piece of the design.
Verify analog IC design using spice simulations
Run Electromigration/IR drop (EMIR) on analog IC layout
Run co-simulation between digital and analog designs
Run Static Timing Analysis (STA) on high speed analog IC design
Develop and enhance flows that support and facilitate robust analog IC design
What We're Looking For
Students have to be in last year of a 5/5.5 year Engineer course at UTN/UNC/IUA or doing Master/PhD in Electrical Engineer at any university of Argentina.• Intuitive and analytical understanding of transistor level and CMOS circuit design
• Experience in Cadence schematics capture, simulation and layout
• Ability to define and adhere to project schedules
• Ability to have effective written and verbal communication skills
• Ability to write behavioral models for both and analog and digital circuits is a plus
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