Director Product Marketing jobs at Marvell

What You Can Expect

• Develop and execute verification plans.
• Create and maintain testbenches and test cases.
• Perform functional and performance verification.
• Debug and resolve design and verification issues.
• Collaborate with design and architecture teams to ensure verification coverage.
• Experience with clock and reset verification is a strong plus.

Other Skills:

• Excellent problem-solving and analytical skills.
• Strong communication and teamwork abilities.
• Ability to mentor junior engineers and lead verification projects.

What We're Looking For

• Bachelor’s degree in Computer Science, Electrical Engineering, or related fields and 4+ years of related professional experience.
• Master’s degree and/or PhD in Computer Science, Electrical Engineering or related fields with 3+ years of experience.
• Proficiency in System Verilog and UVM (Universal Verification Methodology).
• Experience with simulation tools (e.g., VCS).
• Knowledge of scripting languages (Python, Perl, TCL).

Expected Base Pay Range (USD)

The successful candidate’s starting base pay will be determined based on job-related skills, experience, qualifications, work location and market conditions.The expected base pay range for this role may be modified based on market conditions.

Additional Compensation and Benefit Elements

Any applicant who requires a reasonable accommodation during the selection process should contact Marvell HR Helpdesk at

What You Can Expect

• In this role based in Bangalore, you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process.

• You will be responsible for maintaining, enhancing, and supporting Marvell's Place and Route Flow, leveraging industry-standard EDA tools.

• Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks.

• You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues.

• Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level.

• You will need to work across time zones as a part of multisite project execution.

• This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

What We're Looking For

• Completed a Bachelor’s Degree inElectronics/ElectricalEngineering or related fields and have 8-12 years of related professional experience OR a Master’s degree and/or PhD inElectronics/ElectricalEngineering or related fields.

• In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis.

• Good understanding of standard Synthesis to GDS flows and methodology.

• Good scripting skills in languages such as Perl, tcl, and Python.

• Good understanding of digital logic and computer architecture.

• Hands-on experience in advanced technology nodes upto 2nm.

• Strong hands-on experience in blocks/subsystem P&R implementation using Cadence Innovus and Synopsys FC.

• Strong experience in block level signoff power, timing, PV closure & debugging skills.

• Good top level and full-chip experience is an added advantage

• Knowledge of Verilog/VHDL.

• Good communication skills and self-discipline contributing in a team environment.

• Ability to independently drive subsystems/IPs P&R and signoff closure working with global teams.

• Ability to mentor juniors and be involved in team development activities.

What You Can Expect

Marvell is seeking an RF and Analog Design Engineer to contribute to the development of multi-tens of GHz transimpedance amplifiers (TIAs). These optical interface chips are tightly coupled with our high-performance equalizers. The results of our innovative designs have made our TIAs best in class for coherent long-haul and metro systems as well as PAM4 data center systems. In this role you will be responsible for:

• Active-circuit design.
• Design of leading edge transimpedance amplifiers, using both SiGe BiCMOS and the most advanced CMOS FinFET technologies, where circuit performance will need to transcend beyond industry leading products.
• Development of transmission line structures and other millimeter wave structures to enable higher performance than would normally be achievable.
• Design of high-performance broadband analog circuits for optical front-end receivers.
• Design of various other analog circuits including linear regulators, AGC loops, current/voltage sensors, bandgaps etc.
• Work with other functional groups to facilitate post-silicon validation, qualification, transition to mass production, and customer support.

What We're Looking For

• Bachelor’s degree in Electrical Engineering with 3-5 years of industry experience OR Master’s or PhD degree in Electrical Engineering with 1+ years of industry experience in the area of designing high-performance RF/Analog Receiver/TIA.
• Proven experience in high-performance receiver design including both chip tape-out AND lab evaluation.
• Solid experience in.
  • Using EDA CAD tools
  • Performing Analog Custom Layout
• Experience in measuring IC performance and debug of design to correlate simulations to measurements.
• Deep understanding of fundamentals, including:
  • Detailed transistor level design.
  • Device physics.
  • Control/Feedback loop stability analysis.
• Direct project experience in at least one of the following areas is a plus:
  • Automatic gain-control loops.
  • High precision analog circuits including linear regulators, current sensors, bandgaps and DAC/ADC.
  • Continuous-time linear equalizers.
• Experience in Package-System integration issues is desired.
• Project experience in using different technologies. (SiGe BiCMOS and FinFET CMOS are pluses)
• A team-player.
• Experience in the following is a plus:
  • Overseeing and mentoring junior circuit designers.
  • Experience as chip lead with success in silicon.
  • Experience in taking chips to mass production.
  • Ability to translate chip level specifications into architecture.
• Strong communication, presentation and documentation skills.

What You Can Expect

• Responsible for timing constraints developments, synthesis, logic equivalence check, timing closure, timing sign-off of hierarchy blocks and full chip
• Work closely with various multi-functional teams on resolving complex timing issues to ensure successful Tape-out

What We're Looking For

• Thorough knowledge of design timing closure flow and methodology
• At least 3+ years’ experience in timing constraints generation and timing closure. Expertise in STA tools (PrimeTime/Tempus) and flow
• Hands on experience in timing/SDC constraints generation and management for block level and full chip level
• Hands on experience in timing closure for complex SoC design
• Expertise in Synthesis tools (Design Compiler/Fusion Compiler) and flow
• Hands on experience in Synthesis/SDC constraints development for block level and full chip level
• Knowledge of noise and signal integrity effect is a plus
• Knowledge of DFT SDC is a plus
• Experience in synthesis and PnR is a plus
• Experience in CTS and CTS spec development is a plus
• Proficient in scripting languages (TCL and Perl)

Additional Compensation and Benefit Elements

• Competitive salary, plus 13th-month salary and performance-based bonus

• RSUs (Restricted Stock Units) for new joiners and on-going annually

• Premium health & accident insurance for you and your family (spouse and children)

• Annual medical check-up at a designated hospital arranged by Marvell

• Generous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidays

• Exciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more.

What You Can Expect

• As a Senior Director, you’ll be responsible for collaborating with various teams to develop strategies, pushing the IP roadmap, and supporting multiple SOCs.
• This starts at the product definition phase with architecture and marketing then continues through execution of all efforts required including supporting productization.
• You’ll provide leadership in the development of highest value-add IP, subsystem & SoC plans and strategies with cutting edge process, speed and performance designs.
• The planning and execution need to be rationalized with budget and market timing requirements.
• Experience and judgement in determining the value of the tasks defined and executed by the team is important.
• This is a fast-paced, intellectually challenging position, and you’ll work with thought leaders in multiple technology looking for ways to improve the value and quality of the effort while keeping cost in budget.
• Manage and continue to build a team of complex sub-system, co-processors, accelerator and SoC engineers.
• The managed team includes design, verification, and collaborating with the Physical Design, DFT & Validation teams. Develop methodologies and infrastructure with evolving technology challenges including cutting edge semiconductor process, I/O’s, networking bandwidth, embedded cores, and co-processors. Work with architecture, SoCs, software, firmware, program management and post-silicon design teams for plan development and execution.
• Provide technical mentoring for team members. Actively engage in efforts to find improvements in methodologies, techniques, and automation Own schedules and reporting of progress metrics

What We're Looking For

• 25 years of relevant industry experience in Semiconductor design & development
• Demonstrated ability to lead a multi-disciplinary team, show initiative, collaborate and communicate effectively with team members across functions & cultures.
• Experience in all phases of design from concept through productization.
• Understand & appreciate the complexity of data centers, server class or networking chipsets & prior experience with successful first silicon success.
• Ability to recruit and retain engineering talent.
• Demonstrated mentoring of junior staff.
• BS degree or higher in EE or CE or CS with 25+ years or more of RTL and/or verification experience
• 10 + years of experience managing a Design/DV/Emulation & related teams.

Preferred Qualifications:

• Experience with Full chip design, development & emulation of complex designs targeting Datacenters, Servers,Enterprise/Networkingdomain.
• Expert in developing IP, subsystem, Chiplets and SOCs
• Experience with one or more high-speed IO technologies: DDR, PCIe, CXL, Ethernet Management of cross-site teams
• Knowledge of industry standard SOC components (bus fabrics, I/O devices, processors)
• Knowledge of HW-SW co-development and silicon validation cycle