Marvell Sr Director Demand Planning 

United States, California 

30408879

What You Can Expect

• In this role based in Bangalore, you will work with a global team on both the physical design of complex chips as well as the methodology to enable an efficient and robust design process.

• You will be responsible for maintaining, enhancing, and supporting Marvell's Place and Route Flow, leveraging industry-standard EDA tools.

• Your tasks will include performing synthesis, place and route, as well as timing analysis and closure on multiple intermediate and complex logic blocks.

• You will play a crucial role in developing and implementing timing and logic ECOs, collaborating closely with the RTL design team to drive modifications that address congestion and timing issues.

• Additionally, your involvement with the global timing team will include debugging and resolving any block-level timing issues encountered at the partition level.

• You will need to work across time zones as a part of multisite project execution.

• This position provides an exciting platform to engage with diverse engineering challenges within a collaborative and innovative environment at Marvell.

What We're Looking For

• Completed a Bachelor’s Degree inElectronics/ElectricalEngineering or related fields and have 8-12 years of related professional experience OR a Master’s degree and/or PhD inElectronics/ElectricalEngineering or related fields.

• In your coursework, you must have completed a digital logic course and projects that involved circuit design, testing, and timing analysis.

• Good understanding of standard Synthesis to GDS flows and methodology.

• Good scripting skills in languages such as Perl, tcl, and Python.

• Good understanding of digital logic and computer architecture.

• Hands-on experience in advanced technology nodes upto 2nm.

• Strong hands-on experience in blocks/subsystem P&R implementation using Cadence Innovus and Synopsys FC.

• Strong experience in block level signoff power, timing, PV closure & debugging skills.

• Good top level and full-chip experience is an added advantage

• Knowledge of Verilog/VHDL.

• Good communication skills and self-discipline contributing in a team environment.

• Ability to independently drive subsystems/IPs P&R and signoff closure working with global teams.

• Ability to mentor juniors and be involved in team development activities.