Marvell Principal Product Engineer 

United States, California 

371074641

What You Can Expect

• Responsible for timing constraints developments, synthesis, logic equivalence check, timing closure, timing sign-off of hierarchy blocks and full chip
• Work closely with various multi-functional teams on resolving complex timing issues to ensure successful Tape-out

What We're Looking For

• Thorough knowledge of design timing closure flow and methodology
• At least 3+ years’ experience in timing constraints generation and timing closure. Expertise in STA tools (PrimeTime/Tempus) and flow
• Hands on experience in timing/SDC constraints generation and management for block level and full chip level
• Hands on experience in timing closure for complex SoC design
• Expertise in Synthesis tools (Design Compiler/Fusion Compiler) and flow
• Hands on experience in Synthesis/SDC constraints development for block level and full chip level
• Knowledge of noise and signal integrity effect is a plus
• Knowledge of DFT SDC is a plus
• Experience in synthesis and PnR is a plus
• Experience in CTS and CTS spec development is a plus
• Proficient in scripting languages (TCL and Perl)

Additional Compensation and Benefit Elements

• Competitive salary, plus 13th-month salary and performance-based bonus

• RSUs (Restricted Stock Units) for new joiners and on-going annually

• Premium health & accident insurance for you and your family (spouse and children)

• Annual medical check-up at a designated hospital arranged by Marvell

• Generous paid leave policies: 15 annual leave days, 3 Recharge periods per year (company-wide off-work from Friday to Monday), 5 paid sick leave days, 3 days of volunteer time-off and 11 public holidays

• Exciting Employee Events: Participate in fun activities throughout the year such as team birthdays, sports tournaments, company trips, mid-autumn, appreciation week, charity, health seminars, year-end party, and more.