Silicon Packaging Engineering Manager jobs at Intel

Job Description:

• Lead and manage a team of silicon physical design engineers responsible for end-to-end silicon design engineering activities supporting technology development, and product design execution on EMIB 2.5D/3.5D, Foveros S/R/B, and Foveros Direct 3D Intel foundry advanced packaging technologies.

• Oversee planning, scheduling, and execution of design projects, ensuring milestones and deadlines are met.

• Drive continuous improvement in design methodologies, flows, and processes to enhance quality and efficiency.

• Collaborate with cross-functional teams (technology partners, packaging, analysis, and verification) to ensure seamless integration and manufacturability.

• Provide technical leadership and mentorship, fostering a culture of innovation and accountability.

• Responsible for enabling teams to execute through clear goal setting, facilitating work, maintaining accountability, applying differentiated performance management, and driving team results.

• Drives results by inspiring people, role modeling Intel values, developing the capabilities of others, and ensuring a productive work environment.

Key Responsibilities:

Leadership and Management

• Lead and manage a group of Silicon Packaging Engineers, providing guidance, mentorship, and support to ensure the successful execution of projects.

• Oversee the planning, scheduling, and execution of package design projects, ensuring that milestones and deadlines are met.

• Foster a collaborative and innovative team environment, encouraging continuous learning and professional development.

• Lead design groups, coordinating efforts across multiple teams to achieve project goals.

Technical Expertise

• Serve as the technical lead for the package design team cross multiple products.

• Drive the development of advanced packaging designs, ensuring compliance with industry standards and best practices.

• Collaborate with cross-functional teams, including package architects, silicon and board design teams, design rule owners, electrical analysis engineers, and integration teams to define and implement design specifications.

• Leverage extensive experience in advanced packaging designs to meet design KPIs.

• Influence.

• Ensure products are designed and developed with high quality standards by overseeing design processes, risk management, and compliance throughout the product design lifecycle, working closely with cross-functional teams to identify and address potential quality issues before they arise.

Project Management

• Develop and maintain detailed project plans, including resource allocation, risk management, and progress tracking.

• Coordinate with stakeholders to ensure alignment on project goals, deliverables, and timelines.

• Conduct regular project reviews and provide status updates to senior management.

Innovation and Improvement

• Identify and implement process improvements to enhance the efficiency and quality of package designs and development.

• Stay current with industry trends and emerging technologies, incorporating new methodologies and tools into the design process.

• Drive innovation in product design, exploring new approaches and techniques to achieve competitive advantages.

The ideal candidate should exhibit the following behavioral traits:

• Excellent leadership and team management skills, with the ability to inspire and motivate a diverse team of engineers.

• Strong project management skills, with the ability to manage multiple projects simultaneously and meet deadlines.

• Exceptional problem-solving and analytical skills, with a keen attention to detail.

• Excellent communication and interpersonal skills, with the ability to collaborate effectively with cross-functional teams and stakeholders.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in Electrical Engineeringor STEM related field with 9+years of relevant experience

• -OR- Master's degree in Electrical Engineeringor STEM related fieldwith 6+ years ofrelevant experience

• -OR- PhD in Electrical Engineeringor STEM related fieldwith 4+ years of relevant experience

Relevant experience should include the following:

• Experience in silicon design, with at least 3 years in a leadership role.

• Proven experience in a leadership or management role, with a track record of successfully leading engineering teams and delivering complex projects withinestablished timelines.

• Experience with design flows and methodologies (physical design, verification).

• Experience working with EDA tools from Cadence, Synopsys, and/or Siemens.

Preferred Qualifications:

• Experience with advanced nodes and packaging technologies

• Experience in RTL2GDS flows and methodologies

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Responsibilities for this position include, but are not limited to:

• Appliesengineering/technical

• Applies advanced engineering knowledge of Intel and industry technology roadmaps, and technical knowledge of commodities to drive supply chain solutions ahead of Intel's needs.

• Develops supply chain solutions that are tailored to unique Intel development needs for complex situations and products.

• Leverages strong understanding of technology, contracting, negotiating, risk mitigation and supplier relationship management to manage supplier relationships, and provide sustainable cost, quality, availability, and technology solutions with adherence to procurement policies.

• Coordinates purchasing activities with cross-functional teams to acquire materials and services in a cost effective and timely manner.

• Ensures respective commodities meet technical specifications and cost requirements for Intel to develop products/services.

• Works closely with engineering teams and suppliers to define standard and custom product requirements, influences technical design decisions, negotiates technical contract terms with suppliers to meet technical specifications and fulfil business objectives.

• Conducts periodic reviews of commodity sourcing strategies in partnership with engineering teams/customers to shape strategic business objectives and account investments through aligned roadmaps.

• Reviews and pivots sourcing strategies in response to changing market conditions and develops mitigation plans to ensure business continuity.

• Works closely with finance and legal to resolve disputes with suppliers/internal partners.

• Leads sustainability and regularly compliance and ensures suppliers comply with Intel business processes.

• Understands Intel's technical roadmap and positions the supply chain to meet Intel's needs including alignment tosafety/availability/quality/sustainabilityframework.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor’s degree in Engineering, Material Science, Supply Chain Management, or related field with 8+ years relevant experience

— or —

Master’s degree in the same fields with 6+ years of relevant experience

— or —

PhD in the same fields with 4+ years relevant experience

Relevant work experience should be of the following:

• Experience with Supply line and Capacity Management Planning

• Experience with Semiconductor substrate manufacturing, supplier capability analysis and capacity expansion requirements

• Experience with overall semiconductor packaging and advanced packaging requirements

Preferred Qualifications:

• Engineering experience in manufacturing and/or supplier management

• Experience in program management and setting technical recommendations and requirements

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, California, Santa Clara, US, Oregon, Hillsboro
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

Key Responsibilities:

• Lead the co-design of silicon and package, focusing on DDR PHY and mixed signal IP integration for server SOCs.
• Design bump maps, floor plans, and manage area constraints for PHYs, collaborating closely with packaging technical experts.
• Conduct hands-onpackage extractionsand simulations(signal integrity, power integrity)
• Finalize bump-out, floor plan, and area decisions at the end of tech readiness phases.
• Interface with packaging teams on advanced technologies (e.g., C4 bumps, micro bumps, EMIB, hybrid bonding as needed).
• Focus on design, development, and architecture, not process or materials engineering.

Required Experience:

• Experience in both silicon design (preferably mixed signal/analog) and packaging co-design.
• Background in DDR, SOC, or similar high-speed interface development.
• Hands-on expertise with bump mapping, floor planning, and packaging constraints.
• Proven ability to collaborate across silicon and packaging teams, including risk assessment and simulation.
• Familiarity with advanced packaging technologies (hybrid bonding, EMIB, etc.) is a plus but not required.
• Individual contributor or principal engineer level preferred; management experience is not required.
• Experience at leading companies in advanced packaging and PHY design (e.g., Apple, Broadcom, Qualcomm, Micron, AMD, Nvidia).

Qualifications:

• Bachelors in electrical engineering, chemical engineering, mechanical engineering, material science or similar field (Master’s or Ph.D. preferred).
• 10+ years in silicon and packaging co-design

Experienced HireShift 1 (United States of America)US, California, FolsomUS, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

You Are

Responsibilities may include but are not limited to:

• Performs functional verification of CPU logic to ensure design will meet specification requirements.

• Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to CPU microarchitecture specifications.

• Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.

• Replicates, root causes, and debugs issues in the presilicon environment.

• Finds and implements corrective measures to resolve failing tests.

• Collaborates with CPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.

• Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.

• Maintains and improves existing functional verification infrastructure and methodology.

• Participates in the definition of architecture and microarchitecture features of the CPU being designed actively.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications could be obtained through a combination of schoolwork, classes, research, and/or relevant previous job and/or internship experiences.

Minimum Qualifications

• The candidate must have a Bachelor's Degree in Electrical/Computer Engineering or any related field with 4+ years of relevant experience -OR- Master's in Electrical/Computer Engineering or any related field with 3+ years of relevant experience -OR- PhD in Electrical/Computer Engineering or any related field

• 3+ years of experience in Scripting languages such as Python and Perl,

• 3+ years of experience inComputer-Architecturefamiliarity

• 3+ years of experience in Power Management flows including low power entry/exit, frequency change flows etc

• 3+ years of experience in Design Verification and Validation methodologies with UVM, System Verilog and industry standard EDA tools

Preferred Qualifications

• Experience with Pre-silicon verification, SoC validation.

• Proficiency with C/C++ System Verilog coding and debug

• Experience with RTL development

• Knowledge of system level boot flows and power management.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Texas, Austin
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

You Are

Responsibilities may include but are not limited to:

• Performs functional verification of CPU logic to ensure design will meet specification requirements.

• Develops IP verification plans, test benches, and the verification environment to ensure coverage to confirm to CPU microarchitecture specifications.

• Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs.

• Replicates, root causes, and debugs issues in the presilicon environment.

• Finds and implements corrective measures to resolve failing tests.

• Collaborates with CPU architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features and to meet functional, performance, and power goals.

• Documents test plans and drive technical reviews of plans and proofs with design and architecture teams.

• Maintains and improves existing functional verification infrastructure and methodology.

• Participates in the definition of architecture and microarchitecture features of the CPU being designed actively.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Qualifications could be obtained through a combination of schoolwork, classes, research, and/or relevant previous job and/or internship experiences.

Minimum Qualifications

• The candidate must have a Bachelor's Degree in Electrical/Computer Engineering or any related field with 4+ years of relevant experience -OR- Master's in Electrical/Computer Engineering or any related field with 3+ years of relevant experience -OR- PhD in Electrical/Computer Engineering or any related field

• 3+ years of experience in Scripting languages such as Python and Perl,

• 3+ years of experience inComputer-Architecturefamiliarity

• 3+ years of experience in Power Management flows including low power entry/exit, frequency change flows etc

• 3+ years of experience in Design Verification and Validation methodologies with UVM, System Verilog and industry standard EDA tools

Preferred Qualifications

• Experience with Pre-silicon verification, SoC validation.

• Proficiency with C/C++ System Verilog coding and debug

• Experience with RTL development

• Knowledge of system level boot flows and power management.

Experienced HireShift 1 (United States of America)US, Texas, AustinUS, Arizona, Phoenix
Position of Trust

offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

Job Description:

Note: This role requires regular onsite presence to fulfill essential job responsibilities. Performs feasibility studies and provides integrated process solutions to meet desired safety, quality, reliability and output requirements for ultimate transfer to high volume manufacturing. Selects and develops material and equipment for the process to meet quality, reliability, cost, yield, productivity and manufacturability requirements. Plans and conducts experiments to fully characterize the process throughout the development cycle and to improve performance for each specific product. Identifies integrated process solutions to resolve issues or specific requests from customers by partnering with innovators in product engineering and module engineering teams. Conducts new product qualification and technology transfers from fabrication operations. Leverages big data analysis to identify process design weaknesses and/or manufacturing tool issues and proposes corrective, data-based solutions. Collaborates and engages with development and material suppliers, and partners to develop processes and equipment needs to meet technology roadmaps. As a principal engineer, recognized as a domain expert who influences and drives technical direction across Intel and industry. Develops and mentors other technical leaders, grows the community, acts as a change agent, and role models Intel values. Aligns organizational goals with technical vision, formulates technical strategy to deliver leadership solutions, and demonstrates a track record of relentless execution in bringing products and technologies to market.

Qualifications:

Bachelor's degree inElectrical/ElectronicEngineering, &/or Computer Engineering, or Science, or other STEM-related degree and 7 years of progressively related experience.

Alternatively, Master's degree inElectrical/ElectronicEngineering, &/or Computer Engineering, or Science, or other STEM-related degree and 5 years of progressively related experience.

Shift 1 (United States of America)US, Arizona, Phoenix
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

Job Description:

development engineers to drive technology development and enablementacross the full range of patterning modules for advanced CMOS technologies

be responsible fordevelopment and drivingmanufacturability across key lithography tools includingbut not limited to DUV

Primary responsibilities willat the intersection of technology developmenthigh volumeespecially on new lithography processesthat require engineering to meet high volume requirements.

This includes driving safety,quality, performance, throughput, capability (patternand cost.

high volumeand will be

and develop the engineer

The leader will be asubject matter expert and have experience working with Integration and othermodules leaders such as etch and thin films to deliver modular solutionsthat meet the technology targets.

Qualifications:

Minimum qualifications areto be initially considered for this position. Preferred qualifications are in addition to therequirements and are considered a plus factor inMinimum Qualifications:
14 years of relevant work experience in the semiconductor spacewith a strong focus on lithography
Degree in Electrical Engineering or Technical Equivalent
Prior senior management with large, multi-national manufacturing employers, preferably in hightechnology/scientific/semiconductorsectors with prior specialization in technology development.
Strong history of industry experience in process development, leadership, and semiconductor
Background working with a combination of investors and third- party suppliers on solutionoptimization/customizationto meet their manufacturing needsespecially with the industry leaders in lithography solutionssuch as ASML and KT.
Engineering group leader background at global scale including leading significant factory ramp-up and process technology development in high volume manufacturing environments.
Extensive experience instart-up with technicaltrack recordin multiple areas of semi-conductor sector in areas such as manufacturing engineering, quality and reliability, research and development, sourcing/supply chain innovations etc.Preferred Qualifications
Substantial technical background inlithography as used in advanced CMOS technologieswith a body of research and patents.Demonstrated history of delivering customized solutions in Research and Development and HVM organizations.related work experience in a semiconductor foundry preferredRequirements listed would be obtained through a combination of industry relevant job experience, internship

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, Oregon, Hillsboro
Position of TrustThis role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.