Intel Silicon Packaging Design Engineer United States, Arizona, Phoenix 689301013
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As an integral part of Intel's new Integrated Device Manufacturer 2.0 (IDM2.0) strategy, we are establishing Foundry Services (FS), a fully vertical, stand-alone foundry business, reporting directly to the CEO. Foundry Services will be a world-class foundry business and major provider of US and European based capacity to serve customers globally.
Foundry Services will be differentiated from other foundries with a combination of leading-edge packaging and process technology, committed capacity in the US and Europe, and a world-class IP portfolio that customers can choose from, including x86 cores, graphics, media, display, AI, interconnect, fabric and other critical foundational IP's, along with Arm and RISC-V ecosystem IPs. Foundry Services will also provide access to silicon design services to help our customers seamlessly turn silicon into solutions, using industry standard design packages.
This business unit is completely dedicated to the success of its customers with full PandL responsibilities. This model will ensure that our foundry customers' products receive our utmost focus in terms of service, technology enablement, and capacity commitments. FS is already engaged with customers today starting with our existing foundry offerings. We are expanding at a torrid pace to include our most advanced technologies, which are ideal for high-performance applications.
Responsibilities include but are not limited to:
- Drives end to end development for silicon design from concept through tapeout and implements physical layout and routing of the package design.
- Responsible for the definition and development of assembly test chips or bridge die which are used to characterize aspects of chip-package interactions.
- Provides consultation concerning packaging problems and improvements in the packaging process.
- Responds to customer and/or client requests or events as they occur.
- Develops solutions to problems utilizing formal education and judgment.
You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates. Experience listed below would be obtained through a combination of your degree, research and or relevant previous job and or internship experiences.
Minimum Requirements:
- US Citizenship required.
- Ability to obtain and maintain a US Government TS/SCI Security Clearance with Polygraph.
- Bachelor's degree with 1+ years of relevant experience or Master's degree with relevant experience in Mechanical Engineering or Electrical Engineering.Must have the required degree or expect the required degree by December 2025.
- 3+ months experience with microelectronic packageor siliconlayoutdesign usingCadence Virtuoso, Genesys or similar tools.
- 3+ months experience with physical layout aspects of chip design/layout including but not limited to custom layouts, floor plans, schematic generation and schematic to layout conversion and verification.
This position is not eligible for Intel immigration sponsorship.
Preferred Qualifications:
- Active US Government Security Clearance with a minimal of a Secret Level
- Experience with device design, and analog/mixed signal layout
- Experience with ICCompiler and ICWorkbench
- Readiness to troubleshoot a wide variety of physical design/layout issues.
Position of Trust
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
$104,890.00-$148,080.00This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.
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