Intel Physical Design SoC Clock Lead 

United States, Texas 

916312864

Job Description:

As a Physical Design SoC Clock Lead, your responsibilities will include but not limited to:

• Define and develop physical clock architectures, drive clocking designs, and create clocking methodologies and guidelines for IPs or SoCs.
• Define SoC or subsystem level clocking targets and drive design teams to achieve these objectives as required.
• Build simulation models, drive physical implementation, conduct clock analysis, and support power grid methodologies andimplementation.
• Create scalable flows for clocking infrastructure for better performance and power in the design.
• Interact with architecture and IP/SoC design teams to understand clocking requirements and helps them in deciding the right clock distribution methodology based on power and performance requirements.
• Drive overall clock generation and distribution methodology.
• Work with block level designers to implement the clocking techniques for optimizing skew and power.
• Perform jitter analysis and measurements and provide feedback to block level and top-level physical design engineers on key fixes required.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

• Bachelor's degree in Electrical / Computer Engineering, Computer Science or in a STEM related field of study with 5+ years of experience or a Master's degree with 4+ years of relevant experience.
• 4+ years of experience hands-on experience across the entire spectrum of RTL to GDS implementation on advance semiconductor technology nodes and specific challenges in clock design.
• 4+ years of experience in Clocking techniques, static timing analysis (STA), clock domain crossing (CDC) checks, jitter/skew analysis and low-power clocking strategies.

Preferred Qualifications:

• Design Tools, flows and Methods development.
• Previous SoC Clock lead roles.
• Strong leadership and communication skills, ability to plan and work independently and coordinate with cross-functional teams
• Experience with scripting skills in Tcl, Perl, or Python for automation and flow enhancements Understanding of signal integrity, electromigration, and power integrity in the context of clock networks.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and orschoolwork/classes/research.

Experienced HireShift 1 (United States of America)US, California, Santa Clara, US, Massachusetts, Beaver Brook, US, Texas, Austin
Position of Trust

Weoffer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

Annual Salary Range for jobs which could be performed in the US:

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change. The application window for this job posting is expected to end by 04/02/2025