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Your responsibilities may include but not be limited to:
Defines and develops physical clock architecture, drives clocking designs, and creates clocking methodologies and guidelines for IPs or SoCs.
Designs new clocks modules and circuit solutions and implements solutions that meet security and safety compliance for IP or SoC clocking.
Defines SoC or subsystem level clocking targets and drives design teams to achieve these objectives as required.
Build simulation models, drives physical implementation, conducts clock analysis, and supports power grid methodologies and implementation.
Creates scalable flows for clocking infrastructure for better performance and power in the design.
Interacts with architecture and IP/SoC design teams to understand clocking requirements and help them in deciding the right clock distribution methodology based on power and performance requirements.
Proven track record of strong partnership and collaboration with managers, RTL design, architects and other partner teams.
The ideal candidate will also have strong written and verbal communication skills and the ability to drive a team.
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must have a Bachelor's Degree in Computer or Electrical Engineering or related field with 6+ years of relevant experience -OR- a Master’s Degree in Computer or Electrical Engineering or related field with 4+ years of relevant experience -OR- PhD in Computer or Electrical Engineering with 2+ years of relevant experience
2+ years of experience in synthesis, place and route static timing analysis using Primetime tools, DFT flows, and low power design
Preferred Qualifications
Experience in Fusion Compiler and clock distribution tools such as Clock Builder.
Experience as technical leader of SOC/ASIC designs responsible for planning design and physical convergence of SoC clock distribution.
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.These jobs might be a good fit