Intel Physical Design Clock Distribution Engineer United States, California, San Jose 298978103
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Who You Are
Your responsibilities will include but not be limited to:
Defines and develops physical clock architecture, drives clocking designs, and creates clocking methodologies and guidelines for IPs or SoCs.
Designs new clocks modules and circuit solutions and implements solutions that meet security and safety compliance for IP or SoC clocking.
Defines SoC or subsystem level clocking targets and drives design teams to achieve these objectives as required.
Build simulation models, drives physical implementation, conducts clock analysis, and supports power grid methodologies and implementation.
Creates scalable flows for clocking infrastructure for better performance and power in the design.
Interacts with architecture and IP/SoC design teams to understand clocking requirements and help them in deciding the right clock distribution methodology based on power and performance requirements.
Proven track record of strong partnership and collaboration with managers, architecture, RTL design and other partner teams.
In addition to the qualifications listed below, the ideal candidate will also have strong written and verbal communication skills.
You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum Qualifications
The candidate must have a Bachelor's degree in Computer or Electrical Engineering with 4+ years of industry experience -OR- a Master’s Degree in Computer or Electrical Engineering with 3+ years of industry experience.
3+ years of experience with SoC clocking architecture from PLL to partition implementation with Clock Tree Synthesis and have experience with industry standard clock distribution CAD tools such as Clock Builder.
Preferred Qualifications
Experience as technical leader of SOC/ASIC designs responsible for physical clock design and convergence.
Position of Trust
offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:
Annual Salary Range for jobs which could be performed in the US:
This role is available as a fully home-based and generally would require you to attend Intel sites only occasionally based on business need. However, you must live and work from the country specified in the job posting, in which Intel has a legal presence. Due to legal regulations, remote work from any other country is unfortunately not permitted. * Job posting details (such as work model, location or time type) are subject to change. The application window for this job posting is expected to end by 09/15/2025
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