Broadcom ASIC Digital Physical Design Engineer 

United States, California, San Jose 

337083012

Qualifications include:

• MS in Electrical Engineering or Computer Engineering with 10+ years of experience in Physical design or PhD in Electrical Engineering or Computer Engineering with 7+ years of experience in Physical design.

• Deep knowledge about industry standards in Physical Design, Physical aware synthesis, Floor-planning, CTS and place and route.

• Experience in developing and implementing Power-grid and high speed clock constraints and specification.

• Good understanding of physical design verification methodology to debug LVS/DRC issues at the chip and block level.

• Experience with CDC, static timing analysis methodologies and relevant tools.

• Understanding and experience of mixed signal IPs and environments is a must.

• Candidates must be familiar with Innovus, Tempus, PrimeTime, Virtuoso, Caliber & Redhawk (power analysis) tools.

• Good understandingof design tape-outto foundries and solid understanding of supply chain for IC Product development.

• Must have excellent knowledge/experience with TSMC 7nm-2nm, i.e. understanding of power consumptions, area, estimated design and layout efforts for digital blocks, technology limitations.

Highly Desired Qualifications:

- Understanding of backend Cadence tools is must.

- Deep understanding of Signal Integrity and Power Integrity for High Speed designs.

- Excellent time and task management, and interpersonal skills.

Compensation and Benefits

The annual base salary range for this position is $141,000 - $225,000

This position is also eligible for a discretionary annual bonus in accordance with relevant plan documents, and equity in accordance with equity plan documents and equity award agreements.