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Google ASIC Physical Design Lead United States, California, Sunnyvale 28037288
06.03.2025
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
- 10 years experience in ASIC physical design and methodologies in advanced process nodes.
- Experience leading teams through RTL to GDS physical design processes with knowledge of each phase.
- Experience driving place and route on complex designs using industry standard EDA CAD tools, including command execution, debugging, and custom technique development via Tcl or GUI.
- Experience with EMIR parameters and analysis techniques (eg., mitigating EMIR violations and making design tradeoffs related to power grid design and augmentation).
Preferred qualifications:
- Master's degree in Computer Science, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience.
- Experience with IO pads, RDL route, bump mapping, and boundary scan.
- Experience with physical IP integration (e.g. memories, IO's, analog PHYs).
- Experience with silicon interposer design.
- Experience crafting physical design automation flows.
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