Cisco ASIC Physical Design Engineer 

Portugal 

709861969

• Engage in full chip physical implementation, covering the process from RTL to GDSII, and collaborate with Front-End teams to understand design architecture for effective implementation.
• Perform gate-level netlist synthesis (physical synthesis) and execute physical implementation tasks such as floorplanning, placement, Clock Tree Synthesis (CTS), and routing.
• Optimize design for power, performance, and area, and conduct formal verification to ensure design integrity.
• Perform Static Timing Analysis (STA), complete physical verification, and achieve signoff closure.
• Analyze and resolve Electromigration (EM) and IR-drop (IR) issues to meet signoff requirements.

• B.Sc./M.Sc in Electrical Engineering, Computer Science, or any other relevant field.
• Proven experience in ASIC physical design and verification,
• Knowledge and experience in block-level synthesis, place, and route, timing closure.
• Knowledge of industry-standard PnR and signoff tools and their capabilities.

• Deep understanding of all aspects of Physical construction and Integration.
• Knowledge in Physical Design Verification methodology LVS/DRC.
• Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.).
• Understanding of Static Timing Analysis, timing closure, and design constraints.
• Experience in scripting languages like Tcl, Python, Perl.

But “Digital Transformation” is an empty buzz phrase without a culture that allows for innovation, creativity, and yes, even failure (if you learn from it.)