Cisco ASIC Physical Design Engineer 

Armenia, Yerevan 

245171447

• Leverage a solid understanding of physical design flows to develop and maintain efficient and effective design processes.
• Conduct gate-level netlist synthesis to ensure accurate translation of design specifications into a functioning digital circuit.
• Manage the physical implementation process, including floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (PV), to achieve optimal chip layout.
• Carry out static timing analysis to ensure timing constraints are met and facilitate successful signoff closure for design validation.
• Conduct electromigration and IR drop (EMIR) analysis to identify potential reliability issues and ensure signoff closure for design robustness.

You will primarily focus on creating flows, working with EDA tools from different vendors, and performing physical design. You will collaborate with Physical Design and Flow teams. Our members are helpful and aligned, working collaboratively as a cohesive unit. We prioritize teamwork and support where every member contributes to collective success.

• 4+ years minimum of experience in ASIC design.
• Knowledge and experience in block-level synthesis, place, and route, timing closure.
• Knowledge of industry standard PnR and signoff tools and their capabilities.

• Bachelor's or Master's degree in Electrical Engineering, Computer Science, or any other relevant field.
• Understanding of Static Timing Analysis, timing closure, and design constraints.
• Having experience in scripting languages like Tcl, Python, Perl.
• Self-motivated, able to work independently or as a team player.
• Good English verbal and written communication skills.

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