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Cisco Physical Design Engineer Armenia, Yerevan 4508774
09.07.2025
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What You'll Do
- You will be responsible for macro level RTL to gds implementation and signoff.
- Work with Front-End teams to understand the design architecture to ensure optimal physical implementation.
- Execute physical design tasks, including gate-level netlist synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing.
- Optimize designs to achieve industry-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification.
- Conduct Static Timing Analysis (STA), physical verification, formal verification and signoff closure to ensure high-quality results.
- Analyze and resolve Electromigration (EM) and IR-drop (IR) issues, meeting stringent signoff requirements for reliability and performance.
Minimum Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
- 4+ year minimum of hands-on experience in ASIC design and verification
- Proven expertise in ASIC physical design and verification.
- Knowledge of block-level synthesis, place-and-route (PnR), and timing closure.
- First-hand experience with industry-standard PnR and signoff tools such as Synopsys and Cadence.
Preferred Qualifications
- Understanding of all aspects of physical design construction, integration, and methodologies.
- Proficiency in Physical Design Verification, including techniques like LVS and DRC.
- Experience with physical design EDA tools and workflows.
- Expertise in Static Timing Analysis (STA), timing closure, and design constraints.
- Proficiency in scripting languages like Tcl, Python, or Perl, with a focus on automation and efficiency improvements.
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