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Cisco Physical Design Engineer Armenia, Yerevan 189721335
09.07.2025
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What you'll do
- Own the physical design and implementation of full-chip clock mesh networks, within the RTL-to-GDSII flow.
- Implement physical design tasks specifically tailored for clock mesh structures, including custom placement and routing.
- Optimize designs to achieve industry-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification.
- Leverage RCL extraction and HSPICE simulation data to guide physical implementation strategies and layout decisions.
- Analyze and resolve reliability issues, including electromigration (EM), IR drop, and antenna effects, to meet signoff criteria.
- Contribute to the development and maintenance of custom physical design scripts and automation flows to support mesh-specific requirements.
Minimum Qualifications
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field.
- 4+ year minimum of first-hand experience in ASIC design and verification.
- Proven expertise in ASIC physical design and verification.
- Knowledge of block-level synthesis, place-and-route (PnR), and timing closure.
- First-hand experience with industry-standard PnR and signoff tools such as Synopsys and Cadence.
Preferred Qualifications
- Understanding of all aspects of physical design construction, integration, and methodologies.
- Proficiency in Physical Design Verification, including techniques like LVS and DRC.
- Experience with physical design EDA tools and workflows.
- Expertise in Static Timing Analysis (STA), timing closure, and design constraints.
- Proficiency in scripting languages like Tcl, Python, or Perl, with a focus on automation and efficiency improvements.
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