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Job Area:
Engineering Group, Engineering Group > Packaging Engineering
Job responsibilities for this position include package selection, package design, and package EE modeling. This involves optimizing system co-design of IC-PKG-PCB die keeping in mind package footprint/height constraints, IC floor-planning, PCB, high-speed signal integrity, power distribution network, and thermal constraints.
Additional responsibilities:
IC top level floor planning including hard macro block placement, padring, RDL and bump pattern/assignment
System level co-design methodology of IC, Package and PCB/Board
Concept analysis for new product package selection based on requirements for mechanical, thermal and electrical performance with the goal to achieve lowest system level cost
Package design flow methodology implementing high speed interface SI constraints for jitter, IR drop, cross-talk, and SSN specs
Package design flow methodology implementing power distribution network (PDN) constraints for high speed processor cores (1GHz+) including design optimization techniques at the die/pkg/PCB levels
Working with marketing/IC/product teams on competitive analysis and road mapping package technology for future products
Minimum Qualifications:
Bachelor's degree in Engineering, Information Systems, Computer Science, or related field.
2+ years Hardware Engineering experience or related work experience.
This is an office-based position located in San Diego, CA.
Preferred Qualifications:
Working knowledge of IC package and/or PCB selection, design , and layout experience - Experience in Pinmap optimization of optimal PCB design
Working knowledge of die floor planning, IO placement, and bump placement
Working knowledge of Chip, Package and PCB co-design methodology
Experience with high speed SerDes and DDR layout process
Experience in IO + PKG + PCB SI/PI modeling, co-simulation and analysis
Experience in 3D/2D EM simulation tool, electromagnetic theory and transmission line theory
Experience or knowledge in PCB design process like Schematic capture
Familiar with assembly and substrate manufacturing process
Familiar with trade-offs among package cost, technologies, design, performance, power, and thermal requirements.
Familiar with PCB stack-up and breakout strategy
Qualcomm expects its employees to abide by all applicable policies and procedures, including but not limited to security and other requirements regarding protection of Company confidential information and other confidential and/or proprietary information, to the extent those requirements are permissible under applicable law.
Pay range:
$115,500.00 - $173,500.00
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