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Nvidia Timing Methodology Engineer Custom Circuits - New College Grad United States, California 189045217
01.12.2024
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What You'll Be Doing:
- Develop Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones using standard cells and custom designs.
- Validating the timing of custom circuit design using NanoTime and various spice simulations.
- The timing analysis will include the application of variation and statistical parameters in timing-analysis. The QOR data generation will include IR drop, PVT and impact of variation models POCV,AOCV, Moments, wire-variation etc.
- Pursuing or recent completion ofMS or higher in Electrical or Computer Engineering(or equivalent experience).
- Understanding of circuit design and spice simulations.
- Knowledge of advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm and beyond.
- Good understanding of circuit design styles in CMOS: domino circuits, high speed clocking, clock MUXing circuits etc. and how to verify them at circuit level in both spice and transistor level STA.
- Understanding crosstalk, noise, OCV, timing margins, Clocking specs (jitter, IR drop, crosstalk, and spice analysis).
- Experience with coding- TCL, Python. Must have hands-on experience with NanoTime static timing analysis, its algorithms and associated circuit constraint checks.
- Prior experience in ASIC Design and Timing.
- Familiarity with ASIC tools, such as PT.
- Knowledge or experience with Cadence Virtuoso schematics, and .libs in Nanotime as well as PT.
You will also be eligible for equity and .
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