Nvidia Senior Timing Methodology Engineer Custom Circuits 

United States, California 

215898152

What You'll Be Doing:

• Develop Timing sign-off flows, constraints and QOR metrics for custom macro design at transistor level along with ones using standard cells and custom designs.

• Validating the timing of custom circuit design using NanoTime and various spice simulations.

• The timing analysis will include the application of variation and statistical parameters in timing-analysis. The QOR data generation will include IR drop, PVT and impact of variation models POCV,AOCV, Moments, wire-variation etc.

What We Need To See:

• MS (or equivalent experience) in Electrical or Computer Engineering with 5+ years experience in ASIC Design and Timing.

• Proven understanding of circuit design and spice simulations. Hands-on experience in advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm and beyond.

• Good understanding of circuit design styles in CMOS: domino circuits, high speed clocking, clock muxing circuits etc and how to verify them at circuit level in both spice and transistor level sta.

• Understanding crosstalk, noise, OCV, timing margins. Familiarity with Clocking specs: jitter, IR drop, crosstalk, spice analysis. Should have a good understanding of .libs and usage of .libs in Nanotime as well as PT.

• Expertise in coding- TCL, Python. Must have hands-on experience with NanoTime static timing analysis, its algorithms and associated circuit constraint checks. Should be able navigate Cadence Virtuoso schematics. Familiarity with industry standard ASIC tools: PT, etc.

• Strong communications skill and good standout colleague