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What you'll be doing:
Develop and validate flows for PT-STA regression, analysis, QOR metrics for high-speed designs. The focus is on CAD flow development and analysis which is the primary task.
Developflows/recommendations
Collaborate with technology leads, VLSI physical design, and timing engineers to define and deploy the most sophisticated strategies of signing off timing in design for world-class silicon performance.
Develop tools, and methodologies to improve design performance, predictability, and silicon reliability beyond what industry standard tools can offer.
Work on various aspects of STA, constraints, timing and power optimization.
What we need to see:
Pursuing or recent completion of a PhD degree inPhD in Electrical or Computer Engineering (or equivalent experience)
Good knowledge of extraction, device physics, STA methodology and EDA tools limitations. Good understanding of mathematics/physics fundamentals of electrical design.
Clear understanding of low power design techniques such as multi VT, Clock gating, Power gating, Block Activity Power, and Dynamic Voltage-Frequency Scaling (DVFS), CDC, signal/power integrity, etc.
Understanding of 3DIC, stacking, packing, self-heating and its impact on timing/STA closure.
Understanding crosstalk, electro-migration, noise, OCV, timing margins. Familiarity with Clocking specs: jitter, IR drop, crosstalk, spice analysis.
Background of standard cells/memory/IO IP modeling and its usage in the ASIC flow. Hands-on experience in advanced CMOS technologies, design with FinFET technology 5nm/3nm/2nm and beyond.
Ways to stand out from the crowd:
Expertise in coding- TCL, Python. C++ is a plus. Familiarity with industry standard ASIC tools: PT, ICC, Redhawk, Tempus etc.
Prior internships or experience inexperience in ASIC Design and Timing.
You will also be eligible for equity and .
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