Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.
3 years of experience with verification methodologies and languages (e.g., UVM, SystemVerilog).
Experience developing and maintaining verification testbenches, test cases, and test environments.
Experience working on main interconnects, DMA, controllers, and power management, and capturing design specifications in a temporal assertion language (e.g., SVA, PSL).
Preferred qualifications:
Master's degree or PhD in Electrical Engineering or Computer Science.
Knowledge of and experience working with one or more formal verification tools (E.G., JasperGold, VC Formal, Questa Formal, or 360-DV).
Understanding of formal verification algorithms.
Proficiency with scripting languages (e.g. Python).