Bachelor's degree in Electrical Engineering or equivalent practical experience.
8 years of experience in micro-architecture and design of graphics or Machine Learning (ML) Internet Protocols (IP), managing Low Precision/Mixed Precision Numerics.
5 years of experience architecting networking Application-Specific Integrated Circuits (ASIC) from specification to production.
Experience developing Register-Transfer Level (RTL) for ASIC subsystems using SystemVerilog.
Experience in micro-architecture, design, verification, logic synthesis and timing closure.
Preferred qualifications:
PhD degree in Electrical Engineering or equivalent practical experience.
Experience working with software teams optimizing the hardware/software interface.
Experience in performance analysis and modeling, defining and driving performance test plans.
Experience in programming language (e.g., C++, Python, Go).
Knowledge of arithmetic units, bus architectures, accelerators or memory hierarchies and high performance and low power design techniques.