Nvidia SOC Design Top Level Assembly Methodologies Engineer 

United States, California 

258636266

What you'll be doing:

• Be an integral part of the SOC Design team to develop and improve our RTL top-level assembly process and tool set

• Top-level assembly: Test new code/features and Address questions and concerns, in addition to developing guidelines and best practices

• Develop automation software to enable efficient test pattern generation, application of these patterns on Silicon, failure analysis, and yield learning

• Suggest and implement improvements and enhancements to existing flows

• Maintain long term roadmap to address upcoming project challenges for top-level assembly

• Create complex GPU, SOC, and CPU chip configurations. This requires day-to-day interaction with front-end RTL unit designers, back-end physical design engineers, DFT engineers, power architects, software engineers, and world-class engineers from various NVIDIA teams.

What we need to see:

• Bachelors and/or Masters in EE/CE (or equivalent experience)

• 5+ years of shown relevant industry work experience in chip design, specializing in SOC integration and design automation

• Excellent analytical and problem-solving skills.

• Strong object-oriented coding and scripting skills

• Hands-on experience with scripting languages (Perl/Python)

• C++ is highly desired

• Fundamental digital design concepts and experience

• Ability to collaborate with many groups and communicate technical details effectively