In this position, you will participate in our Test Chip design execution, validate and deliver a robust, fully validated reference design and sign off flows, in partnership with EDA vendors and other Intel Foundry partner organizations. You will involve in building the design using the foundry reference flows and continuously improve/update the design to exercise/stretch the flows in various metrics that matter most to our customers. You will help createBachelor of Engineering degree or a Master of Science degree in Electronic, Electrical or Computer Engineering, or equivalent with preferably at least 1 years of experience in SOC/Analog/IP/ASIC design and/or methodology development.Preferred Qualifications:- Minimum 1 years of experience in writing and producing software code using languages such as PERL and TCL.- Minimum 1 years of experience in running Synthesis, Place and Route physical design tools and flow, with demonstrated expertise in design constraints and optimization, timing convergence, low power checks, IR drop analysis and fixes, layout DRC analysis andd fixes, and successful tape-out of designs in advanced nodes.- Experience in Unix/Linux and shell programming.- Experience in 3DIC design will be an added advantage.College GradShift 1 (Malaysia)Malaysia, Penang