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Customer Quality Engineering Leader jobs at Cisco in United States, San Jose
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United States
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San Jose
142 jobs found
06.04.2025
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Cisco ASIC Engineering Technical Leader United States, California, San Jose
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Oversee fullchip SDCs and work with the Physical Design and DFT teams to close fullchip timing in multiple timing modes. Assist with the development of efficient methodology to promote block...
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06.04.2025
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Cisco Leader Application Engineering United States, California, San Jose
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Responsible for the day-to-day activities of the local SDK engineering team. Ensure that software development goals are met and align with the company’s strategic direction. Responsible for grooming the feature...
06.04.2025
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Cisco Senior Mechanical Engineering Technical Leader United States, California, San Jose
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Provide leadership and problem-solving expertise for mechanical testing at a part or system level. Lead/mentor other engineers and convey technical guidance to resolve complex projects/issues. Architect, design, and deliver system...
06.04.2025
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Cisco ASIC Engineering Technical Leader United States, California, San Jose
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You will be leading the CDC/RDC (Clock Domain Crossing / Reset Domain Crossing) methodology in silicon one chips. Design & implement robust and reusable RTL with CDC/RDC considerations. Spec comprehensive...
05.04.2025
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Cisco Regional Sales Leader United States, California, San Francisco
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10+ years selling IT solutions to major accounts preferably in the service provider space. Solid track record of leading large accounts, including forecasting, quota attainment, sales presentations skills, and short/mid/long...
31.03.2025
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Cisco Technical Customer Experience Manager GES West United States, California, San Jose
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Drive adoption of software, services and value realization leading to successful renewal and growth. Proactively manage and mitigate renewal risk throughout customer journey and in alignment with Renewals team, leverage...
30.03.2025
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Cisco Software Engineering Technical Leader United States, California, San Jose
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Bachelors + 12 years of related experience, or Masters + 8 years of related experience, or PhD + 5 years of related experience in an Engineering role. Experience using C++...
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Description:Full job details
Oversee fullchip SDCs and work with the Physical Design and DFT teams to close fullchip timing in multiple timing modes. Assist with the development of efficient methodology to promote block...
These jobs might be a good fit
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