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Google Senior Design Verification Engineer Multimedia Silicon 
Taiwan, New Taipei 
987714621

31.07.2024

Minimum qualifications:
  • Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience.
  • Experience verifying digital logic at RTL using SystemVerilog for ASICs.
  • Experience verifying digital systems using standard IP components/interconnects (e.g., microprocessor cores, hierarchical memory subsystems).
  • Experience with object oriented programming.

Preferred qualifications:
  • Master's degree or PhD in Electrical Engineering, Computer Science, or a related field.
  • Experience creating and using verification components and environments in a standard verification methodology such as UVM.
  • Experience with image processing or other multimedia IPs such as Display or Video Codec.
  • Experience with performance verification of ASICs, ASIC components, and ASIC standard interfaces and memory system architecture.
  • Experience with verification techniques, System Verilog Assertions (SVA) and assertion-based verification.
  • Experience with Gate Level Simulation (GLS), low-power design verification, and support of SoC DV.