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Key Responsibilities
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Act as the primary Bluetooth technical interface to OEM/ODM partners, providing on-site support, issue triage, and design guidance.
Drive Bluetooth features (e.g., LE Audio, Auracast, HDT) across Windows and Chrome OS platforms.
Execute and develop test cases and automation scripts for Bluetooth functionality, performance, interoperability, and user experience.
Reproduce, debug, and root-cause Bluetooth driver, firmware, and platform issues in collaboration with internal development teams.
Own and drive resolution in OEM/ODM bug tracking systems and ensure timely closure with detailed debug logs and analysis.
Analyze customer requirements and feedback, translate them into engineering actions, and influence roadmap and feature priorities.
Deliver technical training, feature overviews, and workshops to customers and internal field teams.
Collaborate cross-functionally with Wi-Fi, platform, and audio teams to ensure seamless connectivity experience on Intel EVO and commercial platforms.
Bachelor's degree or above in Electrical Engineering, Computer Science, or related field.
5+ years of experience with Bluetooth stack, profiles, Controller and RF performance on Windows PCs and Bluetooth products.
Hands-on experience in Bluetooth validation, testing, or debugging on Windows or Chrome OS platforms.
Strong understanding of Bluetooth Classic and Bluetooth Low Energy protocols, profiles (A2DP, HFP, HID, GATT), and LE Audio technologies.
Solid knowledge of Windows OS, driver installation, and log collection (e.g., ETW, WPP, Ellisys, HCI logs).
Proven experience in bug triage and debug collaboration with internal driver/firmware teams and external customers.
Excellent communication skills in English and Mandarin, and ability to work directly with global OEM partners.

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What you'll be doing:
Verify the design and implementation of the industry's leading GPU
Responsible for verification of the Mixed Signal CMOS circuit design, architecture, golden models using advanced verification methodologies
You are expected to understand complex mixed-signal CMOS circuits design and implementation, define the verification scope, develop the verification infrastructure and verify the correctness of the design.
Work closely with Multi-functional teams, circuit and logic design, verification, test engineering to accomplish tasks.
What we need to see:
Pursuing MS/PhD in EE with domain study in analog circuit design / mixed signal circuit design.
Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like HSpice, Finesim, XA)
Experience in crafting test bench environments for component and top level circuit verification
Expertise in System Verilog or similar HVLand strong debugging and analytical skills
Perl and C/C++ programming language experience desirable
Strong communication skills and ability & desire to work as a great teammate are huge plus.

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What you'll be doing:
Be part of an analog team developing high-speed chip interfaces and complex analog functions that enable our graphics processing units (GPU) and SoC products (Tegra)
Design state-of-the-art mixed-signal circuits in deep sub-micron CMOS technologies.
Work closely with physical/layout engineers to floorplan and implement physical design of these functions.
Support debug, characterization and support product through high-volume production.
If you have the dream to learn and explore new technologies and have good analytical skills, this is the ideal position for you.
What we need to see:
You have a MSEE or PhD in Electrical Engineering.
Proven understanding of analog circuit layout concepts in submicron CMOS technologies
You have interests in more than one of the following areas: digital links for display interfaces (such as HDMI, LVDS, DVI, MIPI PHY, Display Port), USB, low-jitter clock synthesis using PLL techniques, IO pads, high-speed serial links, and ADC.
Able to communicate in spoken and written English
Work effectively in a team, good communication skills, enthusiasm and positive energy.
Proficiency in scripting languages like perl, python, skill etc.
Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like HSpice, Finesim, XA)
You are an expert with Cadence custom circuit design tools - particularly virtuoso
Experience running and debugging DRC and LVS with verification tools

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What you'll be doing:
Be part of an analog team building next generation NVLINK.
You will be responsible for the development and implementation of high speed interfaces, including TX/RX/Clocking/PLL.
Work closely with physical/layout engineers to floorplan and implement physical design of these functions.
Support debug, characterization and support product through high-volume production.
What we need to see:
MS / PhD in Electrical Engineering, Computer Engineering or related field with strong analog design background.
CMOS Analog / Mixed Signal Circuit Design Experience in deep sub-micron process (especially in FINFET); Experience with design and verification tools (Cadence's IC design environment, analog circuit simulation tools like Spectre, HSpice, Finesim, XA)
You have interests in more than one of the following areas: digital links for display interfaces (such as HDMI, LVDS, DVI, MIPI PHY, Display Port), USB, low-jitter clock synthesis using PLL techniques, IO pads, high-speed serial links, and ADC.
Able to communicate in spoken and written English
Work effectively in a team, good communication skills, enthusiasm and positive energy.
Proficiency in scripting languages like perl, python, skill etc.
You are an expert with Cadence custom circuit design tools - particularly virtuoso
Experience running and debugging DRC and LVS with verification tools

TEAM OVERVIEW:
KEY RESPONSIBILITIES:
TECHNICAL SKILLS:
REQUIREMENTS/EDUCATION:
These jobs might be a good fit