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Google Multimedia Design Verification Engineer Silicon Taiwan, New Taipei 416797496
24.06.2024
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Minimum qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- Academic coursework in Computer Architecture or Digital Designs.
- Experience with C/C++ or Verilog/SystemVerilog.
Preferred qualifications:
- Master's degree or PhD in Computer Science, Computer Engineering, Electrical Engineering, or a related field.
- 3 years of experience in RTL design or verification.
- Experience in designing/implementing or validating RTL design.
- Experience in a scripting language, C/C++ programming, and software design.
- Knowledge of object-oriented programming.
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