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Google ASIC RTL Design Engineer Machine Learning Accelerators United States, California, Sunnyvale 979662358
04.04.2024
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Minimum qualifications:
Preferred qualifications:
- Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
- Digital design experience using SystemVerilog RTL
Preferred qualifications:
- 3 years of experience in digital design using SystemVerilog or RTL.
- Experience with high-bandwidth bus architectures including control and memory bus architectures, die-to-die interconnects, or inter-chip interconnects.
- Experience interacting with software, system hardware, and other cross-functional teams.
- Experience defining SoC IP interfaces and methodologies.
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