Bachelor's degree in Electrical Engineering, Computer Engineering, or equivalent practical experience.
Digital design experience using SystemVerilog RTL
Preferred qualifications:
3 years of experience in digital design using SystemVerilog or RTL.
Experience with high-bandwidth bus architectures including control and memory bus architectures, die-to-die interconnects, or inter-chip interconnects.
Experience interacting with software, system hardware, and other cross-functional teams.
Experience defining SoC IP interfaces and methodologies.