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Google ASIC RTL Design Engineer Machine Learning Accelerators United States, California, Sunnyvale 348079922
14.08.2024
Info Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Sunnyvale, CA, USA; Madison, WI, USA.Note: By applying to this position you will have an opportunity to share your preferred working location from the following:.
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 5 years of industrial experience such as digital design using SystemVerilog RTL.
- Experience applying engineering best practices (e.g., code review, testing, refactoring).
- Experience applying computer architecture principles to solve open-ended problems.
- Experience in logic design, functional, and PPA closure.
Preferred qualifications:
- Master's degree or PhD in Electrical Engineering, Computer Engineering, or a related field.
- 8 years of experience in ASIC design.
- Experience in one or more successful ASIC products from concept to silicon.
- Understanding in computer architecture/memory subsystem architecture.
- Understanding of computer networks.
- Knowledge of machine learning.
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