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What you’ll be doing:
Verify and implement testing logic of VLSI
Generating test patterns and chip bringup
Develop testing methodology for VLSI
Develop design flow for testing
What we need to see:
Master degree of Electrical Engineering/Computer Engineering/Computer Science
2+ years of DFT or design experiences
Good understanding of Design for Testing including Scan/ATPG/BIST/JTAG
Familiar with Verilog and design tracing.
Experiences with RTL/Gate-level simulation and debugging.
Understanding of Timing is plus
Hands-on experience of In-System Measurement (ISM) circuit is a plus
Skills ofPython/Perl/Tck/C/C++is a plus
Ways to stand out from the crowd:
Fluent English communication is required.
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