Intel IP Enablement Engineer 

United States, Texas 

93251099

About this Role:

This job opportunity will be part of the Ecosystem Technology Office (ETO) group in IFS responsible for enabling IP ecosystem portfolio in support of Intel IDM2.0 strategy and IFS customers.

The selected candidate for this position will be responsible for but not limited to:

• Driving closure of scope in the technical requirements in the RFQ stage, and in the Statement of Work (SoW). Verify IP release criteria defined in the SoW are met and IP is delivered with high quality and on time.
• Managing and driving to resolution technical and schedule dependencies with IP Ecosystem Partners throughout IP development and execution covering pre-silicon and post-silicon.
• Ensuring projects are well planned and executed on time with indicators and communication of project status.
• Identifying and managing risk.
• Work cross-functional dependencies and prioritizing support requests.
• Responsible for IP issue tracking and working with Foundry Design Technology Platform (DTP) team and Technology Development (DT) team to provide prompt feedback and solutions.
• Manage unified messaging between Partners and Intel stakeholders. Build and maintain solid relationships with senior leaders, strategic partners, and 3rd party EDA partners.
• Drive technical support for IFS Ecosystem IP development programs during IP lifecycle: High Speed Serdes IP - PCIe, Ethernet, D2D IP-UCIe, AIB Memory I/F - DDR, LPDDR, HBM- Mixed Signal IP's - ADC, DAC, PLL- and Foundational IP - Embedded memories, Logic Libraries, GPIO.
• Partner with IFS teams as a subject matter expert to facilitate IP development through IP ecosystem partners.
• Influence and drive conflict resolution across stakeholders and vendors for win/win outcomes.

The ideal candidate should exhibit the following behavioral traits:

• Service mindset with a focus on quality solutions.
• Drive velocity of execution and thrive in solving complex problems for customers and suppliers.
• Skills with ecosystem partnership collaborations.
• Excellent project and program management skills to mitigate risk and drive execution to meet schedule commitments in an ambiguous environment.
• Strong communication and presentation skills to executive management.
• Exceptional problem-solving abilities and repertoire of skills.
• Fearless mindset for growth and passion for continuous learning.
• Demonstrate ability to collaborate, influence and drive decisions in a cross-functional setting.
• Adapt and swiftly respond to changes in the business environment.
• Working knowledge of IC Product and Design domains, and familiarity with the Foundry-Fabless model.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications

• Master's degree with 6+ years of Industry experience, or a PhD with 3+ years of Industry experience, in Electrical Engineering or in a STEM related field of study.
• Experience with IP standards i.e. (DDR/LPDDR/HBM, USB, MIPI, PCIe, USB, or HDMI).
• Experience in design and technology tradeoffs for IP i.e.(performance/power/areaand cost).
• Experience in industry standard SOC design signoff methodology.
• Experience in SoC development life cycle including Silicon IP and SoC design, IP/EDA, design methodologies, and product lifecycle (PLC).
• Experience in technical program management of 3rd party IP vendors.

Preferred Qualifications

• IP standards and usage per market segment.
• Experience with Intel process technology or external foundries (TSMC).

Experienced HireShift 1 (United States of America)US, California, Santa ClaraUS, Arizona, Phoenix
Position of Trust

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