Intel IP Enablement Application Engineer 

United States, Texas 

283981712

The Aerospace, Defense and Government (ADG) - SoC Design and IP Enablement Engineer provides technical support to Intel Foundry Services customers on IP integration issues:

• Collaborate with internal teams across Intel and external stakeholders such as foundry customers' design teams, IP providers, and EDA vendors on foundational IP integration issue resolution.
• Create content, application notes and deliver technicaltraining/presentations.
• Drive quality of design kits, documentation, and assist in tearing down barriers to successful customer design tape-outs.
• Able to work independently with design team and customers to solve issues either remotely or onsite.

Your specific responsibilities may include but are not limited to the following:

• Work with cross-functional teams to develop SoC and IP Integration into SoC.
• Engage with IP development team to ensure all IP collaterals are generated and provided.
• Fully own assigned IPs and work with Internal and external customer and help them integrate Intel IPs to SoC and provide technical support.
• Drive resolution of customer issues related to the IP collaterals generation, logic design verification, IP release, and integration in SoC environment. This may involve travel to customer sites.
• Engage in the upfront identification and documentation of customer requirements, working with the IP design teams to disposition requests.
• Prepare customer training materials and provide training on IP architecture, specifications, and fuse/register settings to enable effective debug.
• Debugging, and problem solving in a team environment.

Minimum Qualifications

• US Citizenship required.
• Ability to obtain and maintain a US Government Security Clearance.
• Bachelor's degree in Electrical Engineering, Computer Science, or in a STEM related field of study.
• 3+ years of experience with SOC IP integration.
• 4+ years of experience in RTL design and DFT using Verilog/System Verilog.
• 4+ years of experience with VCS, Verdi, Spyglass or equivalent tools.
• Experience in ASIC or SoC development.

Preferred Qualifications:

• Active US Government Security Clearance with a minimum of Secret level.
• Post Graduate degree in Electrical Engineering, Computer Science, or in a STEM related field of study.
• Experience with one or more industry standard IO interfaces including (ADPLL, GPIO, Digital Thermal Sensors, DDR, LPDDR, PCIE, USB, USB TypeC, Ethernet, etc.)
• Hands on Experience with customer support in at least one of the following domains: (Memory Design, Memory Compiler Design, eFUSE and or antiFUSE.)
• Experience with IP integration and design flow challenges within the context of subsystems and SOCs.
• Experience with IP development.
• Experience in scripting languages like such as Perl/Tcl/ and Python.

Experienced HireShift 1 (United States of America)US, Arizona, PhoenixUS, California, Santa Clara, US, Oregon, Hillsboro
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